mirror of https://gitee.com/openkylin/qemu.git
tcg/s390: Use constant pool for ori
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
bdcd5d1926
commit
4046d9ca04
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@ -225,6 +225,7 @@ typedef enum S390Opcode {
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RXY_LRVH = 0xe31f,
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RXY_LY = 0xe358,
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RXY_NG = 0xe380,
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RXY_OG = 0xe381,
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RXY_STCY = 0xe372,
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RXY_STG = 0xe324,
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RXY_STHY = 0xe370,
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@ -1004,23 +1005,22 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
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}
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}
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static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val)
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static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
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{
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static const S390Opcode oi_insns[4] = {
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RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
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};
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static const S390Opcode nif_insns[2] = {
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static const S390Opcode oif_insns[2] = {
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RIL_OILF, RIL_OIHF
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};
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int i;
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/* Look for no-op. */
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if (val == 0) {
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if (unlikely(val == 0)) {
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return;
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}
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if (s390_facilities & FACILITY_EXT_IMM) {
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/* Try all 32-bit insns that can perform it in one go. */
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for (i = 0; i < 4; i++) {
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tcg_target_ulong mask = (0xffffull << i*16);
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@ -1031,28 +1031,34 @@ static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val)
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}
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/* Try all 48-bit insns that can perform it in one go. */
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if (s390_facilities & FACILITY_EXT_IMM) {
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for (i = 0; i < 2; i++) {
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tcg_target_ulong mask = (0xffffffffull << i*32);
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if ((val & mask) != 0 && (val & ~mask) == 0) {
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tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
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tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
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return;
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}
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}
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}
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/* Use the constant pool if USE_REG_TB, but not for small constants. */
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if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
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if (type == TCG_TYPE_I32) {
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tcg_out_insn(s, RR, OR, dest, TCG_TMP0);
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} else {
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tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);
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}
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} else if (USE_REG_TB) {
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tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
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new_pool_label(s, val, R_390_20, s->code_ptr - 2,
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-(intptr_t)s->code_gen_ptr);
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} else {
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/* Perform the OR via sequential modifications to the high and
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low parts. Do this via recursion to handle 16-bit vs 32-bit
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masks in each half. */
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tgen64_ori(s, dest, val & 0x00000000ffffffffull);
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tgen64_ori(s, dest, val & 0xffffffff00000000ull);
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} else {
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/* With no extended-immediate facility, we don't need to be so
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clever. Just iterate over the insns and mask in the constant. */
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for (i = 0; i < 4; i++) {
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tcg_target_ulong mask = (0xffffull << i*16);
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if ((val & mask) != 0) {
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tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
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}
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}
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tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
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tgen_ori(s, type, dest, val & 0x00000000ffffffffull);
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tgen_ori(s, type, dest, val & 0xffffffff00000000ull);
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}
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}
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@ -1872,7 +1878,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
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if (const_args[2]) {
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tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
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tgen64_ori(s, a0, a2);
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tgen_ori(s, TCG_TYPE_I32, a0, a2);
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} else if (a0 == a1) {
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tcg_out_insn(s, RR, OR, a0, a2);
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} else {
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@ -2104,7 +2110,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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a0 = args[0], a1 = args[1], a2 = args[2];
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if (const_args[2]) {
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tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
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tgen64_ori(s, a0, a2);
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tgen_ori(s, TCG_TYPE_I64, a0, a2);
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} else if (a0 == a1) {
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tcg_out_insn(s, RRE, OGR, a0, a2);
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} else {
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@ -2312,7 +2318,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
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static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
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static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
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static const TCGTargetOpDef r_0_rN = { .args_ct_str = { "r", "0", "rN" } };
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static const TCGTargetOpDef r_0_rM = { .args_ct_str = { "r", "0", "rM" } };
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static const TCGTargetOpDef a2_r
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= { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
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@ -2353,6 +2358,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_sub_i64:
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case INDEX_op_and_i32:
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case INDEX_op_and_i64:
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case INDEX_op_or_i32:
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case INDEX_op_or_i64:
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return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
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case INDEX_op_mul_i32:
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@ -2363,19 +2370,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_mul_i64:
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return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
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case INDEX_op_or_i32:
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/* The use of [iNM] constraints are optimization only, since a full
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64-bit immediate OR can always be performed with 4 sequential
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OI[LH][LH] instructions. By rejecting certain negative ranges,
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the immediate load plus the reg-reg OR is smaller. */
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return (s390_facilities & FACILITY_EXT_IMM
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? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)
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: &r_0_rN);
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case INDEX_op_or_i64:
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return (s390_facilities & FACILITY_EXT_IMM
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? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)
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: &r_0_rN);
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case INDEX_op_xor_i32:
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/* Without EXT_IMM, no immediates are supported. Otherwise,
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rejecting certain negative ranges leads to smaller code. */
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