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target/arm: Implement MVE DLSTP 

Implement the MVE DLSTP insn; this is like the existing DLS
insn, except that it must do an FPU access check and it
sets LTPSIZE to the value specified in the insn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-06-14 16:09:18 +01:00
parent 6822abfdf8
commit 40a36f003c
2 changed files with 27 additions and 5 deletions
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9
target/arm/t32.decode
View File

@ -671,14 +671,17 @@ BL 1111 0. .......... 11.1 ............ @branch24
# LE and WLS immediate
%lob_imm 1:10 11:1 !function=times_2
DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001
DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 size=4
WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm size=4
{
LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
# This is WLSTP
WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=%lob_imm
}
LCTP 1111 0 0000 000 1111 1110 0000 0000 0001
{
LCTP 1111 0 0000 000 1111 1110 0000 0000 0001
# This is DLSTP
DLS 1111 0 0000 0 size:2 rn:4 1110 0000 0000 0001
}
]
}

23
target/arm/translate.c
View File

@ -8114,13 +8114,32 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
return false;
}
if (a->rn == 13 || a->rn == 15) {
/* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
/*
* For DLSTP rn == 15 is a related encoding (LCTP); the
* other cases caught by this condition are all
* CONSTRAINED UNPREDICTABLE: we choose to UNDEF
*/
return false;
}
/* Not a while loop, no tail predication: just set LR to the count */
if (a->size != 4) {
/* DLSTP */
if (!dc_isar_feature(aa32_mve, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
}
/* Not a while loop: set LR to the count, and set LTPSIZE for DLSTP */
tmp = load_reg(s, a->rn);
store_reg(s, 14, tmp);
if (a->size != 4) {
/* DLSTP: set FPSCR.LTPSIZE */
tmp = tcg_const_i32(a->size);
store_cpu_field(tmp, v7m.ltpsize);
}
return true;
}