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target/mips: Update ITU to handle bus errors 

Update ITU to handle bus errors.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim 2019-01-03 16:50:54 +01:00 committed by Aleksandar Markovic
parent 043715d1e0
commit 40cd718052
1 changed files with 22 additions and 0 deletions
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22
hw/misc/mips_itu.c
View File

@ -375,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c)
view_pv_common_write(c);
}
static void raise_exception(int excp)
{
current_cpu->exception_index = excp;
cpu_loop_exit(current_cpu);
}
static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
{
MIPSITUState *s = (MIPSITUState *)opaque;
@ -382,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
ITCView view = get_itc_view(addr);
uint64_t ret = -1;
switch (size) {
case 1:
case 2:
s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
raise_exception(EXCP_DBE);
return 0;
}
switch (view) {
case ITCVIEW_BYPASS:
ret = view_bypass_read(cell);
@ -420,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
ITCStorageCell *cell = get_cell(s, addr);
ITCView view = get_itc_view(addr);
switch (size) {
case 1:
case 2:
s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
raise_exception(EXCP_DBE);
return;
}
switch (view) {
case ITCVIEW_BYPASS:
view_bypass_write(cell, data);