mirror of https://gitee.com/openkylin/qemu.git
pc: acpi: q35: move ISA bridge into SSDT
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Igor Mammedov
Michael S. Tsirkin
parent
78e1ad0509
commit
41f95a5200
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@ -1633,8 +1633,21 @@ static void build_piix4_pci0_int(Aml *table)
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static void build_q35_pci0_int(Aml *table)
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static void build_q35_pci0_int(Aml *table)
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{
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{
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Aml *field;
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Aml *sb_scope = aml_scope("_SB");
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Aml *sb_scope = aml_scope("_SB");
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field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
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aml_append(field, aml_named_field("PRQA", 8));
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aml_append(field, aml_named_field("PRQB", 8));
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aml_append(field, aml_named_field("PRQC", 8));
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aml_append(field, aml_named_field("PRQD", 8));
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aml_append(field, aml_reserved_field(0x20));
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aml_append(field, aml_named_field("PRQE", 8));
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aml_append(field, aml_named_field("PRQF", 8));
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aml_append(field, aml_named_field("PRQG", 8));
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aml_append(field, aml_named_field("PRQH", 8));
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aml_append(sb_scope, field);
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aml_append(sb_scope, build_irq_status_method());
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aml_append(sb_scope, build_irq_status_method());
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aml_append(sb_scope, build_iqcr_method(false));
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aml_append(sb_scope, build_iqcr_method(false));
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@ -1663,6 +1676,46 @@ static void build_q35_pci0_int(Aml *table)
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aml_append(table, sb_scope);
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aml_append(table, sb_scope);
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}
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}
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static void build_q35_isa_bridge(Aml *table)
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{
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Aml *dev;
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Aml *scope;
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Aml *field;
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scope = aml_scope("_SB.PCI0");
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dev = aml_device("ISA");
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aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
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/* ICH9 PCI to ISA irq remapping */
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aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
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0x60, 0x0C));
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aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
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0x80, 0x02));
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field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
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aml_append(field, aml_named_field("COMA", 3));
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aml_append(field, aml_reserved_field(1));
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aml_append(field, aml_named_field("COMB", 3));
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aml_append(field, aml_reserved_field(1));
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aml_append(field, aml_named_field("LPTD", 2));
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aml_append(field, aml_reserved_field(2));
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aml_append(field, aml_named_field("FDCD", 2));
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aml_append(dev, field);
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aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
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0x82, 0x02));
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/* enable bits */
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field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
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aml_append(field, aml_named_field("CAEN", 1));
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aml_append(field, aml_named_field("CBEN", 1));
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aml_append(field, aml_named_field("LPEN", 1));
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aml_append(field, aml_named_field("FDEN", 1));
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aml_append(dev, field);
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aml_append(scope, dev);
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aml_append(table, scope);
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}
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static void build_piix4_pm(Aml *table)
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static void build_piix4_pm(Aml *table)
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{
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{
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Aml *dev;
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Aml *dev;
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@ -1790,6 +1843,7 @@ build_ssdt(GArray *table_data, GArray *linker,
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build_piix4_pci0_int(ssdt);
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build_piix4_pci0_int(ssdt);
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} else {
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} else {
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build_hpet_aml(ssdt);
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build_hpet_aml(ssdt);
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build_q35_isa_bridge(ssdt);
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build_isa_devices_aml(ssdt);
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build_isa_devices_aml(ssdt);
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build_q35_pci0_int(ssdt);
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build_q35_pci0_int(ssdt);
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}
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}
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@ -113,39 +113,6 @@ DefinitionBlock (
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}
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}
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}
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}
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/****************************************************************
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* LPC ISA bridge
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****************************************************************/
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Scope(\_SB.PCI0) {
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/* PCI D31:f0 LPC ISA bridge */
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Device(ISA) {
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Name (_ADR, 0x001F0000) // _ADR: Address
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/* ICH9 PCI to ISA irq remapping */
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OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
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OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
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Field(LPCD, AnyAcc, NoLock, Preserve) {
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COMA, 3,
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, 1,
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COMB, 3,
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Offset(0x01),
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LPTD, 2,
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, 2,
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FDCD, 2
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}
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OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
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Field(LPCE, AnyAcc, NoLock, Preserve) {
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CAEN, 1,
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CBEN, 1,
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LPEN, 1,
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FDEN, 1
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}
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}
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}
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/****************************************************************
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/****************************************************************
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* PCI IRQs
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* PCI IRQs
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****************************************************************/
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****************************************************************/
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@ -285,19 +252,6 @@ DefinitionBlock (
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}
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}
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}
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}
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Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
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PRQA, 8,
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PRQB, 8,
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PRQC, 8,
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PRQD, 8,
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Offset(0x08),
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PRQE, 8,
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PRQF, 8,
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PRQG, 8,
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PRQH, 8
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}
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External(LNKA, DeviceObj)
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External(LNKA, DeviceObj)
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External(LNKB, DeviceObj)
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External(LNKB, DeviceObj)
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External(LNKC, DeviceObj)
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External(LNKC, DeviceObj)
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