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hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1 

When C_CTRL.CBPR is 1, the Non-Secure view of C_BPR is altered:
  - A Non-Secure read of C_BPR should return the BPR value plus 1,
  saturated to 7,
  - A Non-Secure write should be ignored.

Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
Message-id: 20180119145756.7629-6-luc.michel@greensocs.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed comment typo]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc MICHEL 2018-01-25 11:45:30 +00:00 committed by Peter Maydell
parent fc05a6f22a
commit 421a3c224e
1 changed files with 13 additions and 3 deletions
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10
hw/intc/arm_gic.c
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@ -1212,8 +1212,13 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
break;
case 0x08: /* Binary Point */
if (s->security_extn && !attrs.secure) {
if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {
/* NS view of BPR when CBPR is 1 */
*data = MIN(s->bpr[cpu] + 1, 7);
} else {
/* BPR is banked. Non-secure copy stored in ABPR. */
*data = s->abpr[cpu];
}
} else {
*data = s->bpr[cpu];
}
@ -1286,7 +1291,12 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
break;
case 0x08: /* Binary Point */
if (s->security_extn && !attrs.secure) {
if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {
/* WI when CBPR is 1 */
return MEMTX_OK;
} else {
s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
}
} else {
s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR);
}