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target/arm: Split out rebuild_hflags_common_32 

Create a function to compute the values of the TBFLAG_A32 bits
that will be cached, and are used by all profiles.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191023150057.25731-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-10-23 11:00:36 -04:00 committed by Peter Maydell
parent d4d7503ac6
commit 43eccfb6ed
1 changed files with 11 additions and 5 deletions
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16
target/arm/helper.c
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@ -11070,6 +11070,15 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
return flags; return flags;
} }
static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx, uint32_t flags)
{
flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
ARMMMUIdx mmu_idx) ARMMMUIdx mmu_idx)
{ {
@ -11141,7 +11150,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
ARMMMUIdx mmu_idx = arm_mmu_idx(env); ARMMMUIdx mmu_idx = arm_mmu_idx(env);
int current_el = arm_current_el(env); int current_el = arm_current_el(env);
int fp_el = fp_exception_el(env, current_el); int fp_el = fp_exception_el(env, current_el);
uint32_t flags = 0; uint32_t flags;
if (is_a64(env)) { if (is_a64(env)) {
*pc = env->pc; *pc = env->pc;
@ -11151,12 +11160,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
} }
} else { } else {
*pc = env->regs[15]; *pc = env->regs[15];
flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);
flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);
flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
@ -11166,8 +11174,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TBFLAG_A32, flags = FIELD_DP32(flags, TBFLAG_A32,
XSCALE_CPAR, env->cp15.c15_cpar); XSCALE_CPAR, env->cp15.c15_cpar);
} }
flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
} }
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine