openkylin
/
qemu
mirror of https://gitee.com/openkylin/qemu.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

target-tricore: Make TRICORE_FEATURES implying others. 

Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C 1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction was first introduced.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann 2014-11-13 14:17:08 +00:00
parent 0974257ed5
commit 47e04430ed
2 changed files with 12 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
target-tricore/cpu.c
View File

@ -63,8 +63,17 @@ static bool tricore_cpu_has_work(CPUState *cs)
static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
{ {
CPUState *cs = CPU(dev); CPUState *cs = CPU(dev);
TriCoreCPU *cpu = TRICORE_CPU(dev);
TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev); TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
CPUTriCoreState *env = &cpu->env;
/* Some features automatically imply others */
if (tricore_feature(env, TRICORE_FEATURE_16)) {
set_feature(env, TRICORE_FEATURE_131);
}
if (tricore_feature(env, TRICORE_FEATURE_131)) {
set_feature(env, TRICORE_FEATURE_13);
}
cpu_reset(cs); cpu_reset(cs);
qemu_init_vcpu(cs); qemu_init_vcpu(cs);

6
target-tricore/translate.c
View File

@ -2206,17 +2206,17 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_CACHEI_WI_SHORTOFF: case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF: case OPC2_32_BO_CACHEI_W_SHORTOFF:
/* TODO: Raise illegal opcode trap, /* TODO: Raise illegal opcode trap,
if tricore_feature(TRICORE_FEATURE_13) */ if !tricore_feature(TRICORE_FEATURE_131) */
break; break;
case OPC2_32_BO_CACHEI_W_POSTINC: case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC: case OPC2_32_BO_CACHEI_WI_POSTINC:
if (!tricore_feature(env, TRICORE_FEATURE_13)) { if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
} /* TODO: else raise illegal opcode trap */ } /* TODO: else raise illegal opcode trap */
break; break;
case OPC2_32_BO_CACHEI_W_PREINC: case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC: case OPC2_32_BO_CACHEI_WI_PREINC:
if (!tricore_feature(env, TRICORE_FEATURE_13)) { if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
} /* TODO: else raise illegal opcode trap */ } /* TODO: else raise illegal opcode trap */
break; break;