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x86: avoid AREG0 for misc helpers 

Add an explicit CPUX86State parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2012-04-29 18:42:47 +00:00
parent 329e607d8e
commit 4a7443be52
4 changed files with 84 additions and 83 deletions
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1
target-i386/Makefile.objs
View File

@ -7,6 +7,5 @@ obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-$(CONFIG_LINUX_USER) += ioport-user.o
obj-$(CONFIG_BSD_USER) += ioport-user.o
$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
$(obj)/seg_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)

40
target-i386/helper.h
View File

@ -41,12 +41,12 @@ DEF_HELPER_4(lcall_protected, void, int, tl, int, int)
DEF_HELPER_1(iret_real, void, int)
DEF_HELPER_2(iret_protected, void, int, int)
DEF_HELPER_2(lret_protected, void, int, int)
DEF_HELPER_1(read_crN, tl, int)
DEF_HELPER_2(write_crN, void, int, tl)
DEF_HELPER_1(lmsw, void, tl)
DEF_HELPER_2(read_crN, tl, env, int)
DEF_HELPER_3(write_crN, void, env, int, tl)
DEF_HELPER_2(lmsw, void, env, tl)
DEF_HELPER_1(clts, void, env)
DEF_HELPER_2(movl_drN_T0, void, int, tl)
DEF_HELPER_1(invlpg, void, tl)
DEF_HELPER_3(movl_drN_T0, void, env, int, tl)
DEF_HELPER_2(invlpg, void, env, tl)
DEF_HELPER_3(enter_level, void, int, int, tl)
#ifdef TARGET_X86_64
@ -58,10 +58,10 @@ DEF_HELPER_1(sysexit, void, int)
DEF_HELPER_1(syscall, void, int)
DEF_HELPER_1(sysret, void, int)
#endif
DEF_HELPER_1(hlt, void, int)
DEF_HELPER_1(monitor, void, tl)
DEF_HELPER_1(mwait, void, int)
DEF_HELPER_0(debug, void)
DEF_HELPER_2(hlt, void, env, int)
DEF_HELPER_2(monitor, void, env, tl)
DEF_HELPER_2(mwait, void, env, int)
DEF_HELPER_1(debug, void, env)
DEF_HELPER_1(reset_rf, void, env)
DEF_HELPER_3(raise_interrupt, void, env, int, int)
DEF_HELPER_2(raise_exception, void, env, int)
@ -72,22 +72,22 @@ DEF_HELPER_1(reset_inhibit_irq, void, env)
DEF_HELPER_2(boundw, void, tl, int)
DEF_HELPER_2(boundl, void, tl, int)
DEF_HELPER_1(rsm, void, env)
DEF_HELPER_1(into, void, int)
DEF_HELPER_2(into, void, env, int)
DEF_HELPER_1(cmpxchg8b, void, tl)
#ifdef TARGET_X86_64
DEF_HELPER_1(cmpxchg16b, void, tl)
#endif
DEF_HELPER_0(single_step, void)
DEF_HELPER_0(cpuid, void)
DEF_HELPER_0(rdtsc, void)
DEF_HELPER_0(rdtscp, void)
DEF_HELPER_0(rdpmc, void)
DEF_HELPER_0(rdmsr, void)
DEF_HELPER_0(wrmsr, void)
DEF_HELPER_1(single_step, void, env)
DEF_HELPER_1(cpuid, void, env)
DEF_HELPER_1(rdtsc, void, env)
DEF_HELPER_1(rdtscp, void, env)
DEF_HELPER_1(rdpmc, void, env)
DEF_HELPER_1(rdmsr, void, env)
DEF_HELPER_1(wrmsr, void, env)
DEF_HELPER_1(check_iob, void, i32)
DEF_HELPER_1(check_iow, void, i32)
DEF_HELPER_1(check_iol, void, i32)
DEF_HELPER_2(check_iob, void, env, i32)
DEF_HELPER_2(check_iow, void, env, i32)
DEF_HELPER_2(check_iol, void, env, i32)
DEF_HELPER_2(outb, void, i32, i32)
DEF_HELPER_1(inb, tl, i32)
DEF_HELPER_2(outw, void, i32, i32)

77
target-i386/misc_helper.c
View File

@ -18,16 +18,11 @@
*/
#include "cpu.h"
#include "dyngen-exec.h"
#include "ioport.h"
#include "helper.h"
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
/* check if Port I/O is allowed in TSS */
static inline void check_io(int addr, int size)
static inline void check_io(CPUX86State *env, int addr, int size)
{
int io_offset, val, mask;
@ -37,13 +32,13 @@ static inline void check_io(int addr, int size)
env->tr.limit < 103) {
goto fail;
}
io_offset = lduw_kernel(env->tr.base + 0x66);
io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
io_offset += (addr >> 3);
/* Note: the check needs two bytes */
if ((io_offset + 1) > env->tr.limit) {
goto fail;
}
val = lduw_kernel(env->tr.base + io_offset);
val = cpu_lduw_kernel(env, env->tr.base + io_offset);
val >>= (addr & 7);
mask = (1 << size) - 1;
/* all bits must be zero to allow the I/O */
@ -53,19 +48,19 @@ static inline void check_io(int addr, int size)
}
}
void helper_check_iob(uint32_t t0)
void helper_check_iob(CPUX86State *env, uint32_t t0)
{
check_io(t0, 1);
check_io(env, t0, 1);
}
void helper_check_iow(uint32_t t0)
void helper_check_iow(CPUX86State *env, uint32_t t0)
{
check_io(t0, 2);
check_io(env, t0, 2);
}
void helper_check_iol(uint32_t t0)
void helper_check_iol(CPUX86State *env, uint32_t t0)
{
check_io(t0, 4);
check_io(env, t0, 4);
}
void helper_outb(uint32_t port, uint32_t data)
@ -98,7 +93,7 @@ target_ulong helper_inl(uint32_t port)
return cpu_inl(port);
}
void helper_into(int next_eip_addend)
void helper_into(CPUX86State *env, int next_eip_addend)
{
int eflags;
@ -108,7 +103,7 @@ void helper_into(int next_eip_addend)
}
}
void helper_single_step(void)
void helper_single_step(CPUX86State *env)
{
#ifndef CONFIG_USER_ONLY
check_hw_breakpoints(env, 1);
@ -117,7 +112,7 @@ void helper_single_step(void)
raise_exception(env, EXCP01_DB);
}
void helper_cpuid(void)
void helper_cpuid(CPUX86State *env)
{
uint32_t eax, ebx, ecx, edx;
@ -131,20 +126,20 @@ void helper_cpuid(void)
}
#if defined(CONFIG_USER_ONLY)
target_ulong helper_read_crN(int reg)
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
return 0;
}
void helper_write_crN(int reg, target_ulong t0)
void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
}
void helper_movl_drN_T0(int reg, target_ulong t0)
void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
}
#else
target_ulong helper_read_crN(int reg)
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
target_ulong val;
@ -164,7 +159,7 @@ target_ulong helper_read_crN(int reg)
return val;
}
void helper_write_crN(int reg, target_ulong t0)
void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
switch (reg) {
@ -189,7 +184,7 @@ void helper_write_crN(int reg, target_ulong t0)
}
}
void helper_movl_drN_T0(int reg, target_ulong t0)
void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
int i;
@ -211,21 +206,21 @@ void helper_movl_drN_T0(int reg, target_ulong t0)
}
#endif
void helper_lmsw(target_ulong t0)
void helper_lmsw(CPUX86State *env, target_ulong t0)
{
/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
if already set to one. */
t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
helper_write_crN(0, t0);
helper_write_crN(env, 0, t0);
}
void helper_invlpg(target_ulong addr)
void helper_invlpg(CPUX86State *env, target_ulong addr)
{
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
tlb_flush_page(env, addr);
}
void helper_rdtsc(void)
void helper_rdtsc(CPUX86State *env)
{
uint64_t val;
@ -239,13 +234,13 @@ void helper_rdtsc(void)
EDX = (uint32_t)(val >> 32);
}
void helper_rdtscp(void)
void helper_rdtscp(CPUX86State *env)
{
helper_rdtsc();
helper_rdtsc(env);
ECX = (uint32_t)(env->tsc_aux);
}
void helper_rdpmc(void)
void helper_rdpmc(CPUX86State *env)
{
if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
raise_exception(env, EXCP0D_GPF);
@ -258,15 +253,15 @@ void helper_rdpmc(void)
}
#if defined(CONFIG_USER_ONLY)
void helper_wrmsr(void)
void helper_wrmsr(CPUX86State *env)
{
}
void helper_rdmsr(void)
void helper_rdmsr(CPUX86State *env)
{
}
#else
void helper_wrmsr(void)
void helper_wrmsr(CPUX86State *env)
{
uint64_t val;
@ -413,7 +408,7 @@ void helper_wrmsr(void)
}
}
void helper_rdmsr(void)
void helper_rdmsr(CPUX86State *env)
{
uint64_t val;
@ -554,7 +549,7 @@ void helper_rdmsr(void)
}
#endif
static void do_hlt(void)
static void do_hlt(CPUX86State *env)
{
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
env->halted = 1;
@ -562,15 +557,15 @@ static void do_hlt(void)
cpu_loop_exit(env);
}
void helper_hlt(int next_eip_addend)
void helper_hlt(CPUX86State *env, int next_eip_addend)
{
cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
EIP += next_eip_addend;
do_hlt();
do_hlt(env);
}
void helper_monitor(target_ulong ptr)
void helper_monitor(CPUX86State *env, target_ulong ptr)
{
if ((uint32_t)ECX != 0) {
raise_exception(env, EXCP0D_GPF);
@ -579,7 +574,7 @@ void helper_monitor(target_ulong ptr)
cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
}
void helper_mwait(int next_eip_addend)
void helper_mwait(CPUX86State *env, int next_eip_addend)
{
if ((uint32_t)ECX != 0) {
raise_exception(env, EXCP0D_GPF);
@ -592,11 +587,11 @@ void helper_mwait(int next_eip_addend)
/* more than one CPU: do not sleep because another CPU may
wake this one */
} else {
do_hlt();
do_hlt(env);
}
}
void helper_debug(void)
void helper_debug(CPUX86State *env)
{
env->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);

49
target-i386/translate.c
View File

@ -740,9 +740,15 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
state_saved = 1;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
switch (ot) {
case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
case 0:
gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
break;
case 1:
gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
break;
case 2:
gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
break;
}
}
if(s->flags & HF_SVMI_MASK) {
@ -2736,7 +2742,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip)
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
gen_helper_debug();
gen_helper_debug(cpu_env);
s->is_jmp = DISAS_TB_JUMP;
}
@ -2753,9 +2759,9 @@ static void gen_eob(DisasContext *s)
gen_helper_reset_rf(cpu_env);
}
if (s->singlestep_enabled) {
gen_helper_debug();
gen_helper_debug(cpu_env);
} else if (s->tf) {
gen_helper_single_step();
gen_helper_single_step(cpu_env);
} else {
tcg_gen_exit_tb(0);
}
@ -6832,7 +6838,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_into(tcg_const_i32(s->pc - pc_start));
gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start));
break;
#ifdef WANT_ICEBP
case 0xf1: /* icebp (undocumented, exits to external debugger) */
@ -6989,9 +6995,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
gen_helper_rdmsr();
gen_helper_rdmsr(cpu_env);
} else {
gen_helper_wrmsr();
gen_helper_wrmsr(cpu_env);
}
}
break;
@ -7001,7 +7007,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
gen_jmp_im(pc_start - s->cs_base);
if (use_icount)
gen_io_start();
gen_helper_rdtsc();
gen_helper_rdtsc(cpu_env);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@ -7011,7 +7017,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_rdpmc();
gen_helper_rdpmc(cpu_env);
break;
case 0x134: /* sysenter */
/* For Intel SYSENTER is valid on 64-bit */
@ -7065,7 +7071,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_cpuid();
gen_helper_cpuid(cpu_env);
break;
case 0xf4: /* hlt */
if (s->cpl != 0) {
@ -7074,7 +7080,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start));
s->is_jmp = DISAS_TB_JUMP;
}
break;
@ -7186,7 +7192,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
gen_op_andl_A0_ffff();
}
gen_add_A0_ds_seg(s);
gen_helper_monitor(cpu_A0);
gen_helper_monitor(cpu_env, cpu_A0);
break;
case 1: /* mwait */
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
@ -7194,7 +7200,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
goto illegal_op;
gen_update_cc_op(s);
gen_jmp_im(pc_start - s->cs_base);
gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start));
gen_eob(s);
break;
default:
@ -7334,7 +7340,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
gen_helper_lmsw(cpu_T[0]);
gen_helper_lmsw(cpu_env, cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
}
@ -7348,7 +7354,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(pc_start - s->cs_base);
gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
gen_helper_invlpg(cpu_A0);
gen_helper_invlpg(cpu_env, cpu_A0);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
}
@ -7383,7 +7389,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
gen_jmp_im(pc_start - s->cs_base);
if (use_icount)
gen_io_start();
gen_helper_rdtscp();
gen_helper_rdtscp(cpu_env);
if (use_icount) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@ -7565,11 +7571,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
gen_jmp_im(pc_start - s->cs_base);
if (b & 2) {
gen_op_mov_TN_reg(ot, 0, rm);
gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
gen_op_mov_reg_T0(ot, rm);
}
break;
@ -7598,7 +7605,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
gen_op_mov_TN_reg(ot, 0, rm);
gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {