mirror of https://gitee.com/openkylin/qemu.git
target-xtensa: implement FP1 group
These are comparison and conditional move opcodes. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -49,4 +49,12 @@ DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32)
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DEF_HELPER_3(itof, f32, env, i32, i32)
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DEF_HELPER_3(uitof, f32, env, i32, i32)
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DEF_HELPER_4(un_s, void, env, i32, f32, f32)
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DEF_HELPER_4(oeq_s, void, env, i32, f32, f32)
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DEF_HELPER_4(ueq_s, void, env, i32, f32, f32)
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DEF_HELPER_4(olt_s, void, env, i32, f32, f32)
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DEF_HELPER_4(ult_s, void, env, i32, f32, f32)
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DEF_HELPER_4(ole_s, void, env, i32, f32, f32)
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DEF_HELPER_4(ule_s, void, env, i32, f32, f32)
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#include "def-helper.h"
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@ -858,3 +858,50 @@ float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
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return float32_scalbn(uint32_to_float32(v, &env->fp_status),
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(int32_t)scale, &env->fp_status);
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}
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static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
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{
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if (v) {
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env->sregs[BR] |= br;
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} else {
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env->sregs[BR] &= ~br;
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}
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}
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void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
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{
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set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
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}
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void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
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{
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set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
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}
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void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
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{
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int v = float32_compare_quiet(a, b, &env->fp_status);
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set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
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}
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void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
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{
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set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
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}
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void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
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{
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int v = float32_compare_quiet(a, b, &env->fp_status);
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set_br(env, v == float_relation_less || v == float_relation_unordered, br);
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}
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void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
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{
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set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
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}
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void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
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{
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int v = float32_compare_quiet(a, b, &env->fp_status);
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set_br(env, v != float_relation_greater, br);
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}
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@ -2019,7 +2019,86 @@ static void disas_xtensa_insn(DisasContext *dc)
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case 11: /*FP1*/
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HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
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TBD();
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#define gen_compare(rel, br, a, b) \
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do { \
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TCGv_i32 bit = tcg_const_i32(1 << br); \
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\
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gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
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tcg_temp_free(bit); \
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} while (0)
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switch (OP2) {
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case 1: /*UN.Sf*/
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gen_compare(un_s, RRR_R, RRR_S, RRR_T);
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break;
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case 2: /*OEQ.Sf*/
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gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
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break;
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case 3: /*UEQ.Sf*/
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gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
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break;
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case 4: /*OLT.Sf*/
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gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
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break;
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case 5: /*ULT.Sf*/
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gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
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break;
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case 6: /*OLE.Sf*/
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gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
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break;
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case 7: /*ULE.Sf*/
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gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
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break;
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#undef gen_compare
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case 8: /*MOVEQZ.Sf*/
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case 9: /*MOVNEZ.Sf*/
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case 10: /*MOVLTZ.Sf*/
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case 11: /*MOVGEZ.Sf*/
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gen_window_check1(dc, RRR_T);
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{
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static const TCGCond cond[] = {
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TCG_COND_NE,
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TCG_COND_EQ,
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TCG_COND_GE,
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TCG_COND_LT
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};
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int label = gen_new_label();
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tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
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tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
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gen_set_label(label);
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}
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break;
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case 12: /*MOVF.Sf*/
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case 13: /*MOVT.Sf*/
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HAS_OPTION(XTENSA_OPTION_BOOLEAN);
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{
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int label = gen_new_label();
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
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tcg_gen_brcondi_i32(
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OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE,
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tmp, 0, label);
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tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
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gen_set_label(label);
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tcg_temp_free(tmp);
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}
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break;
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default: /*reserved*/
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RESERVED();
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break;
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}
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break;
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default: /*reserved*/
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