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riscv: plic: Set msi_nonbroken as true 

Set msi_nonbroken as true for the PLIC.

According to the comment located here:
https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
the msi_nonbroken variable should be set to true even if they don't
support MSI. In this case that is what we are doing as we don't support
MSI.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Andrea Bolognani <abologna@redhat.com>
Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
Message-Id: <256afbb2da005dc62c159b0f4a4fc0d95c050660.1552679970.git.alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Alistair Francis 2019-03-15 20:05:36 +00:00 committed by Paolo Bonzini
parent 9164add701
commit 4f5604c41d
1 changed files with 3 additions and 0 deletions
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3
hw/riscv/sifive_plic.c
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@ -22,6 +22,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/sifive_plic.h"
@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
msi_nonbroken = true;
}
static void sifive_plic_class_init(ObjectClass *klass, void *data)