mirror of https://gitee.com/openkylin/qemu.git
MIPS queue for October 1st, 2019
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJdk2xzAAoJENSXKoln91plW9MIAIDoaE9LXhYnlK1JgORP40kk oWQXQvZ8kt2hUJfddaAGCOzVIcTuWKEeWGS3kPGE31kTS9F16w1SybVji0nxfn+R ESK1K0uqUj785Mt/mQTNm9+6741RN6GCeTac+s8afjyn2vw2wWWyS1BhILPNu3fh ezu0SzM+EIlD8r/201jOSucVOCQp5X8RZWp89Ne4ys2wIN1g4dnUZBbIZPH4tSRQ a3SfLrPWBwXREQ94+BAHJ+Doqw0frwBXOf4hs6d2nKwiwZrJ3ktM1XX6+Rke/hGC BiNo5dEtUyMWK1YGcznFfI0Mthn8AueEEu9YX5rmNwdvyx4BwzxTIm1UOihcqHA= =+FaI -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-01-2019' into staging MIPS queue for October 1st, 2019 # gpg: Signature made Tue 01 Oct 2019 16:10:43 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-01-2019: target/mips: msa: Move helpers for <AND|NOR|OR|XOR>.V target/mips: msa: Simplify and move helper for MOVE.V target/mips: msa: Split helpers for MOD_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for DIV_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for CLT_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for CLE_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for CEQ.<B|H|W|D> target/mips: msa: Split helpers for AVER_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for AVE_<S|U>.<B|H|W|D> target/mips: msa: Split helpers for B<CLR|NEG|SEL>.<B|H|W|D> target/mips: msa: Unroll loops and demacro <BMNZ|BMZ|BSEL>.V target/mips: msa: Split helpers for BINS<L|R>.<B|H|W|D> target/mips: msa: Split helpers for PCNT.<B|H|W|D> target/mips: msa: Split helpers for <NLOC|NLZC>.<B|H|W|D> target/mips: Clean up translate.c target/mips: Clean up mips-defs.h target/mips: Clean up kvm_mips.h target/mips: Clean up internal.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
4f59102571
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@ -777,6 +777,123 @@ DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
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DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
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/* MIPS SIMD Architecture */
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DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)
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DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)
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DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)
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DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)
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DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)
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DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
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DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
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DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
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DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)
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DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
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DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)
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DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)
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DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
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DEF_HELPER_3(msa_move_v, void, env, i32, i32)
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DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32)
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@ -815,9 +932,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_bclr_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_bset_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_bneg_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32)
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@ -828,19 +942,10 @@ DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_ceq_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_clt_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_clt_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_cle_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_cle_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_ave_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_ave_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_aver_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_aver_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
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@ -850,10 +955,6 @@ DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_div_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_div_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_mod_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_mod_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32)
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@ -882,7 +983,6 @@ DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
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DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
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DEF_HELPER_3(msa_move_v, void, env, i32, i32)
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DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32)
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@ -926,17 +1026,7 @@ DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32)
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DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
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DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
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@ -1,4 +1,5 @@
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/* mips internal definitions and helpers
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/*
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* MIPS internal definitions and helpers
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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@ -9,8 +10,10 @@
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#include "fpu/softfloat-helpers.h"
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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/*
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* MMU types, the first four entries have the same layout as the
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* CP0C0_MT field.
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*/
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enum mips_mmu_types {
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MMU_TYPE_NONE,
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MMU_TYPE_R4000,
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@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
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!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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/* Note that the TCStatus IXMT field is initialized to zero,
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and only MT capable cores can set it to one. So we don't
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need to check for MT capabilities here. */
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/*
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* Note that the TCStatus IXMT field is initialized to zero,
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* and only MT capable cores can set it to one. So we don't
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* need to check for MT capabilities here.
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*/
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!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
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}
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@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
|
|||
status = env->CP0_Status & CP0Ca_IP_mask;
|
||||
|
||||
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
|
||||
/* A MIPS configured with a vectorizing external interrupt controller
|
||||
will feed a vector into the Cause pending lines. The core treats
|
||||
the status lines as a vector level, not as indiviual masks. */
|
||||
/*
|
||||
* A MIPS configured with a vectorizing external interrupt controller
|
||||
* will feed a vector into the Cause pending lines. The core treats
|
||||
* the status lines as a vector level, not as indiviual masks.
|
||||
*/
|
||||
r = pending > status;
|
||||
} else {
|
||||
/* A MIPS configured with compatibility or VInt (Vectored Interrupts)
|
||||
treats the pending lines as individual interrupt lines, the status
|
||||
lines are individual masks. */
|
||||
/*
|
||||
* A MIPS configured with compatibility or VInt (Vectored Interrupts)
|
||||
* treats the pending lines as individual interrupt lines, the status
|
||||
* lines are individual masks.
|
||||
*/
|
||||
r = (pending & status) != 0;
|
||||
}
|
||||
return r;
|
||||
|
|
@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env)
|
|||
active = 0;
|
||||
}
|
||||
|
||||
/* Now verify that there are active thread contexts in the VPE.
|
||||
|
||||
This assumes the CPU model will internally reschedule threads
|
||||
if the active one goes to sleep. If there are no threads available
|
||||
the active one will be in a sleeping state, and we can turn off
|
||||
the entire VPE. */
|
||||
/*
|
||||
* Now verify that there are active thread contexts in the VPE.
|
||||
*
|
||||
* This assumes the CPU model will internally reschedule threads
|
||||
* if the active one goes to sleep. If there are no threads available
|
||||
* the active one will be in a sleeping state, and we can turn off
|
||||
* the entire VPE.
|
||||
*/
|
||||
if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
|
||||
/* TC is not activated. */
|
||||
active = 0;
|
||||
|
|
@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env)
|
|||
if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
|
||||
!(env->CP0_Status & (1 << CP0St_ERL)) &&
|
||||
!(env->hflags & MIPS_HFLAG_DM)) {
|
||||
env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
|
||||
env->hflags |= (env->CP0_Status >> CP0St_KSU) &
|
||||
MIPS_HFLAG_KSU;
|
||||
}
|
||||
#if defined(TARGET_MIPS64)
|
||||
if ((env->insn_flags & ISA_MIPS3) &&
|
||||
|
|
@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env)
|
|||
env->hflags |= MIPS_HFLAG_COP1X;
|
||||
}
|
||||
} else if (env->insn_flags & ISA_MIPS4) {
|
||||
/* All supported MIPS IV CPUs use the XX (CU3) to enable
|
||||
and disable the MIPS IV extensions to the MIPS III ISA.
|
||||
Some other MIPS IV CPUs ignore the bit, so the check here
|
||||
would be too restrictive for them. */
|
||||
/*
|
||||
* All supported MIPS IV CPUs use the XX (CU3) to enable
|
||||
* and disable the MIPS IV extensions to the MIPS III ISA.
|
||||
* Some other MIPS IV CPUs ignore the bit, so the check here
|
||||
* would be too restrictive for them.
|
||||
*/
|
||||
if (env->CP0_Status & (1U << CP0St_CU3)) {
|
||||
env->hflags |= MIPS_HFLAG_COP1X;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*
|
||||
* Copyright (C) 2012-2014 Imagination Technologies Ltd.
|
||||
* Authors: Sanjay Lal <sanjayl@kymasys.com>
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifndef KVM_MIPS_H
|
||||
#define KVM_MIPS_H
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
#ifndef QEMU_MIPS_DEFS_H
|
||||
#define QEMU_MIPS_DEFS_H
|
||||
|
||||
/* If we want to use host float regs... */
|
||||
//#define USE_HOST_FLOAT_REGS
|
||||
/*
|
||||
* If we want to use host float regs...
|
||||
*
|
||||
* #define USE_HOST_FLOAT_REGS
|
||||
*/
|
||||
|
||||
/* Real pages are variable size... */
|
||||
#define MIPS_TLB_MAX 128
|
||||
|
|
@ -57,43 +60,46 @@
|
|||
#define ASE_MXU 0x0200000000000000ULL
|
||||
|
||||
/* MIPS CPU defines. */
|
||||
#define CPU_MIPS1 (ISA_MIPS1)
|
||||
#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
|
||||
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
|
||||
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
|
||||
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
|
||||
#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
|
||||
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
|
||||
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
|
||||
#define CPU_MIPS1 (ISA_MIPS1)
|
||||
#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
|
||||
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
|
||||
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
|
||||
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
|
||||
#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
|
||||
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
|
||||
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
|
||||
|
||||
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
|
||||
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
|
||||
|
||||
/* MIPS Technologies "Release 1" */
|
||||
#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
|
||||
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
|
||||
#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
|
||||
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
|
||||
|
||||
/* MIPS Technologies "Release 2" */
|
||||
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
|
||||
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
|
||||
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
|
||||
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
|
||||
|
||||
/* MIPS Technologies "Release 3" */
|
||||
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
|
||||
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
||||
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
|
||||
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
|
||||
|
||||
/* MIPS Technologies "Release 5" */
|
||||
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
|
||||
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
|
||||
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
|
||||
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
|
||||
|
||||
/* MIPS Technologies "Release 6" */
|
||||
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
|
||||
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
|
||||
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
|
||||
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
|
||||
|
||||
/* Wave Computing: "nanoMIPS" */
|
||||
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
|
||||
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
|
||||
|
||||
/* Strictly follow the architecture standard:
|
||||
- Disallow "special" instruction handling for PMON/SPIM.
|
||||
Note that we still maintain Count/Compare to match the host clock. */
|
||||
//#define MIPS_STRICT_STANDARD 1
|
||||
/*
|
||||
* Strictly follow the architecture standard:
|
||||
* - Disallow "special" instruction handling for PMON/SPIM.
|
||||
* Note that we still maintain Count/Compare to match the host clock.
|
||||
*
|
||||
* #define MIPS_STRICT_STANDARD 1
|
||||
*/
|
||||
|
||||
#endif /* QEMU_MIPS_DEFS_H */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
tcg_gen_andi_tl(arg, arg, ~0xffff);
|
||||
register_name = "BadInstrX";
|
||||
break;
|
||||
default:
|
||||
default:
|
||||
goto cp0_unimplemented;
|
||||
}
|
||||
break;
|
||||
|
|
@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
case CP0_REG31__KSCRATCH6:
|
||||
CP0_CHECK(ctx->kscrexist & (1 << sel));
|
||||
tcg_gen_ld_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
|
||||
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
|
||||
tcg_gen_ext32s_tl(arg, arg);
|
||||
register_name = "KScratch";
|
||||
break;
|
||||
|
|
@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
case CP0_REG31__KSCRATCH6:
|
||||
CP0_CHECK(ctx->kscrexist & (1 << sel));
|
||||
tcg_gen_st_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
|
||||
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
|
||||
register_name = "KScratch";
|
||||
break;
|
||||
default:
|
||||
|
|
@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
break;
|
||||
case CP0_REG01__YQMASK:
|
||||
CP0_CHECK(ctx->insn_flags & ASE_MT);
|
||||
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
|
||||
tcg_gen_ld_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_YQMask));
|
||||
register_name = "YQMask";
|
||||
break;
|
||||
case CP0_REG01__VPESCHEDULE:
|
||||
CP0_CHECK(ctx->insn_flags & ASE_MT);
|
||||
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
|
||||
tcg_gen_ld_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_VPESchedule));
|
||||
register_name = "VPESchedule";
|
||||
break;
|
||||
case CP0_REG01__VPESCHEFBACK:
|
||||
CP0_CHECK(ctx->insn_flags & ASE_MT);
|
||||
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
|
||||
tcg_gen_ld_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_VPEScheFBack));
|
||||
register_name = "VPEScheFBack";
|
||||
break;
|
||||
case CP0_REG01__VPEOPT:
|
||||
|
|
@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
case CP0_REGISTER_02:
|
||||
switch (sel) {
|
||||
case CP0_REG02__ENTRYLO0:
|
||||
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
|
||||
tcg_gen_ld_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_EntryLo0));
|
||||
register_name = "EntryLo0";
|
||||
break;
|
||||
case CP0_REG02__TCSTATUS:
|
||||
|
|
@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
|
||||
register_name = "Config5";
|
||||
break;
|
||||
/* 6,7 are implementation dependent */
|
||||
/* 6,7 are implementation dependent */
|
||||
case CP0_REG16__CONFIG6:
|
||||
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
|
||||
register_name = "Config6";
|
||||
|
|
@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
}
|
||||
break;
|
||||
case CP0_REGISTER_21:
|
||||
/* Officially reserved, but sel 0 is used for R1x000 framemask */
|
||||
/* Officially reserved, but sel 0 is used for R1x000 framemask */
|
||||
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
|
||||
switch (sel) {
|
||||
case 0:
|
||||
|
|
@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
case CP0_REG31__KSCRATCH6:
|
||||
CP0_CHECK(ctx->kscrexist & (1 << sel));
|
||||
tcg_gen_ld_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
|
||||
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
|
||||
register_name = "KScratch";
|
||||
break;
|
||||
default:
|
||||
|
|
@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
break;
|
||||
case CP0_REG01__VPESCHEDULE:
|
||||
CP0_CHECK(ctx->insn_flags & ASE_MT);
|
||||
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
|
||||
tcg_gen_st_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_VPESchedule));
|
||||
register_name = "VPESchedule";
|
||||
break;
|
||||
case CP0_REG01__VPESCHEFBACK:
|
||||
CP0_CHECK(ctx->insn_flags & ASE_MT);
|
||||
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
|
||||
tcg_gen_st_tl(arg, cpu_env,
|
||||
offsetof(CPUMIPSState, CP0_VPEScheFBack));
|
||||
register_name = "VPEScheFBack";
|
||||
break;
|
||||
case CP0_REG01__VPEOPT:
|
||||
|
|
@ -28380,15 +28386,300 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
|
|||
TCGv_i32 twt = tcg_const_i32(wt);
|
||||
|
||||
switch (MASK_MSA_3R(ctx->opcode)) {
|
||||
case OPC_BINSL_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_BINSR_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_BCLR_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_bclr_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_bclr_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_bclr_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_bclr_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_BNEG_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_bneg_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_bneg_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_bneg_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_bneg_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_BSET_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_bset_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_bset_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_bset_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_bset_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_AVE_S_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_AVE_U_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_AVER_S_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_AVER_U_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_CEQ_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_ceq_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_ceq_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_ceq_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_ceq_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_CLE_S_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_CLE_U_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_CLT_S_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_CLT_U_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DIV_S_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_div_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_div_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_div_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_div_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DIV_U_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_div_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_div_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_div_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_div_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_MOD_S_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_MOD_U_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_SLL_df:
|
||||
gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ADDV_df:
|
||||
gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_CEQ_df:
|
||||
gen_helper_msa_ceq_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ADD_A_df:
|
||||
gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
|
|
@ -28431,9 +28722,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
|
|||
case OPC_MAX_S_df:
|
||||
gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_CLT_S_df:
|
||||
gen_helper_msa_clt_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ADDS_S_df:
|
||||
gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
|
|
@ -28449,15 +28737,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
|
|||
case OPC_SRLR_df:
|
||||
gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_BCLR_df:
|
||||
gen_helper_msa_bclr_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MAX_U_df:
|
||||
gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_CLT_U_df:
|
||||
gen_helper_msa_clt_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ADDS_U_df:
|
||||
gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
|
|
@ -28467,75 +28749,33 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
|
|||
case OPC_PCKOD_df:
|
||||
gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_BSET_df:
|
||||
gen_helper_msa_bset_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MIN_S_df:
|
||||
gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_CLE_S_df:
|
||||
gen_helper_msa_cle_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_AVE_S_df:
|
||||
gen_helper_msa_ave_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ASUB_S_df:
|
||||
gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_DIV_S_df:
|
||||
gen_helper_msa_div_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ILVL_df:
|
||||
gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_BNEG_df:
|
||||
gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MIN_U_df:
|
||||
gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_CLE_U_df:
|
||||
gen_helper_msa_cle_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_AVE_U_df:
|
||||
gen_helper_msa_ave_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ASUB_U_df:
|
||||
gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_DIV_U_df:
|
||||
gen_helper_msa_div_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ILVR_df:
|
||||
gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_BINSL_df:
|
||||
gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MAX_A_df:
|
||||
gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_AVER_S_df:
|
||||
gen_helper_msa_aver_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MOD_S_df:
|
||||
gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ILVEV_df:
|
||||
gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_BINSR_df:
|
||||
gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MIN_A_df:
|
||||
gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_AVER_U_df:
|
||||
gen_helper_msa_aver_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_MOD_U_df:
|
||||
gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
case OPC_ILVOD_df:
|
||||
gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
|
||||
break;
|
||||
|
|
@ -28952,14 +29192,53 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
|
|||
#endif
|
||||
gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
|
||||
break;
|
||||
case OPC_PCNT_df:
|
||||
gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws);
|
||||
break;
|
||||
case OPC_NLOC_df:
|
||||
gen_helper_msa_nloc_df(cpu_env, tdf, twd, tws);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_nloc_b(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_nloc_h(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_nloc_w(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_nloc_d(cpu_env, twd, tws);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_NLZC_df:
|
||||
gen_helper_msa_nlzc_df(cpu_env, tdf, twd, tws);
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_nlzc_b(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_nlzc_h(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_nlzc_w(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_nlzc_d(cpu_env, twd, tws);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_PCNT_df:
|
||||
switch (df) {
|
||||
case DF_BYTE:
|
||||
gen_helper_msa_pcnt_b(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_HALF:
|
||||
gen_helper_msa_pcnt_h(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_WORD:
|
||||
gen_helper_msa_pcnt_w(cpu_env, twd, tws);
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
gen_helper_msa_pcnt_d(cpu_env, twd, tws);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
MIPS_INVAL("MSA instruction");
|
||||
|
|
|
|||
Loading…
Reference in New Issue