mirror of https://gitee.com/openkylin/qemu.git
hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
This simple mux sits between the PLL channels and the DSI0E and DSI0P clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel and outputs the selected signal to source number 4 of DSI0E/P clock muxes. It is controlled by the cm_dsi0hsck register. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -339,6 +339,58 @@ static const TypeInfo cprman_clock_mux_info = {
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};
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/* DSI0HSCK mux */
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static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s)
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{
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bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD);
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Clock *src = src_is_plld ? s->plld_in : s->plla_in;
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clock_update(s->out, clock_get(src));
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}
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static void dsi0hsck_mux_in_update(void *opaque)
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{
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dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque));
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}
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static void dsi0hsck_mux_init(Object *obj)
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{
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CprmanDsi0HsckMuxState *s = CPRMAN_DSI0HSCK_MUX(obj);
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DeviceState *dev = DEVICE(obj);
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s->plla_in = qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_update, s);
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s->plld_in = qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_update, s);
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static const VMStateDescription dsi0hsck_mux_vmstate = {
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.name = TYPE_CPRMAN_DSI0HSCK_MUX,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState),
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VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &dsi0hsck_mux_vmstate;
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}
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static const TypeInfo cprman_dsi0hsck_mux_info = {
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.name = TYPE_CPRMAN_DSI0HSCK_MUX,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CprmanDsi0HsckMuxState),
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.class_init = dsi0hsck_mux_class_init,
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.instance_init = dsi0hsck_mux_init,
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};
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/* CPRMAN "top level" model */
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static uint32_t get_cm_lock(const BCM2835CprmanState *s)
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@ -501,6 +553,10 @@ static void cprman_write(void *opaque, hwaddr offset,
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case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
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update_mux_from_cm(s, idx);
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break;
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case R_CM_DSI0HSCK:
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dsi0hsck_mux_update(&s->dsi0hsck_mux);
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break;
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}
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}
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@ -540,6 +596,8 @@ static void cprman_reset(DeviceState *dev)
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device_cold_reset(DEVICE(&s->channels[i]));
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}
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device_cold_reset(DEVICE(&s->dsi0hsck_mux));
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
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device_cold_reset(DEVICE(&s->clock_muxes[i]));
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}
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@ -565,6 +623,10 @@ static void cprman_init(Object *obj)
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set_pll_channel_init_info(s, &s->channels[i], i);
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}
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object_initialize_child(obj, "dsi0hsck-mux",
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&s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX);
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s->dsi0hsck_mux.reg_cm = &s->regs[R_CM_DSI0HSCK];
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
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char *alias;
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@ -612,7 +674,7 @@ static void connect_mux_sources(BCM2835CprmanState *s,
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if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) {
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src = s->gnd;
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} else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) {
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src = s->gnd; /* TODO */
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src = s->dsi0hsck_mux.out;
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} else if (i < CPRMAN_CLOCK_SRC_PLLA) {
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src = CLK_SRC_MAPPING[i];
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} else {
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@ -650,6 +712,15 @@ static void cprman_realize(DeviceState *dev, Error **errp)
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}
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}
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clock_set_source(s->dsi0hsck_mux.plla_in,
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s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out);
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clock_set_source(s->dsi0hsck_mux.plld_in,
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s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out);
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if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) {
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return;
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}
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
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CprmanClockMuxState *clock_mux = &s->clock_muxes[i];
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@ -700,6 +771,7 @@ static void cprman_register_types(void)
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type_register_static(&cprman_pll_info);
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type_register_static(&cprman_pll_channel_info);
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type_register_static(&cprman_clock_mux_info);
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type_register_static(&cprman_dsi0hsck_mux_info);
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}
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type_init(cprman_register_types);
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@ -174,6 +174,20 @@ typedef struct CprmanClockMuxState {
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struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
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} CprmanClockMuxState;
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typedef struct CprmanDsi0HsckMuxState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanClockMux id;
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uint32_t *reg_cm;
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Clock *plla_in;
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Clock *plld_in;
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Clock *out;
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} CprmanDsi0HsckMuxState;
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struct BCM2835CprmanState {
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/*< private >*/
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SysBusDevice parent_obj;
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@ -184,6 +198,7 @@ struct BCM2835CprmanState {
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CprmanPllState plls[CPRMAN_NUM_PLL];
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CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
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CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
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CprmanDsi0HsckMuxState dsi0hsck_mux;
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uint32_t regs[CPRMAN_NUM_REGS];
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uint32_t xosc_freq;
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@ -15,6 +15,7 @@
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#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
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#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
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#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
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#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
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DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
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TYPE_CPRMAN_PLL)
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@ -22,6 +23,8 @@ DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
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TYPE_CPRMAN_PLL_CHANNEL)
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DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
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TYPE_CPRMAN_CLOCK_MUX)
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DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX,
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TYPE_CPRMAN_DSI0HSCK_MUX)
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/* Register map */
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@ -223,6 +226,9 @@ REG32(CM_LOCK, 0x114)
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FIELD(CM_LOCK, FLOCKB, 9, 1)
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FIELD(CM_LOCK, FLOCKA, 8, 1)
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REG32(CM_DSI0HSCK, 0x120)
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FIELD(CM_DSI0HSCK, SELPLLD, 0, 1)
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/*
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* This field is common to all registers. Each register write value must match
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* the CPRMAN_PASSWORD magic value in its 8 MSB.
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