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target-mips: Fix ALIGN instruction when bp=0 

If executing ALIGN with shift count bp=0 within mips64 emulation,
the result of the operation should be sign extended.

Taken from the official documentation (pseudo code) :

ALIGN:
	tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
	tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
	tmp = tmp_rt_hi || tmp_rt_lo
	GPR[rd] = sign_extend.32(tmp)

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Miodrag Dinic 2015-12-03 16:48:57 +01:00 committed by Leon Alrae
parent 1aa56f6ee7
commit 51243852af
1 changed files with 10 additions and 1 deletions
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11
target-mips/translate.c
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@ -4630,7 +4630,16 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
t0 = tcg_temp_new(); t0 = tcg_temp_new();
gen_load_gpr(t0, rt); gen_load_gpr(t0, rt);
if (bp == 0) { if (bp == 0) {
tcg_gen_mov_tl(cpu_gpr[rd], t0); switch (opc) {
case OPC_ALIGN:
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
break;
#if defined(TARGET_MIPS64)
case OPC_DALIGN:
tcg_gen_mov_tl(cpu_gpr[rd], t0);
break;
#endif
}
} else { } else {
TCGv t1 = tcg_temp_new(); TCGv t1 = tcg_temp_new();
gen_load_gpr(t1, rs); gen_load_gpr(t1, rs);