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target/arm: Add ID register values for Cortex-M0 

Give the Cortex-M0 ID register values corresponding to its
implemented behaviour.  These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation.  We use the same
values that the Cortex-M3 does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-09-10 18:38:54 +01:00
parent d20c3ebda2
commit 51cb228a1d
1 changed files with 24 additions and 0 deletions
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24
target/arm/cpu_tcg.c
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@ -256,6 +256,30 @@ static void cortex_m0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M);
cpu->midr = 0x410cc200;
/*
* These ID register values are not guest visible, because
* we do not implement the Main Extension. They must be set
* to values corresponding to the Cortex-M0's implemented
* features, because QEMU generally controls its emulation
* by looking at ID register fields. We use the same values as
* for the M3.
*/
cpu->isar.id_pfr0 = 0x00000030;
cpu->isar.id_pfr1 = 0x00000200;
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
cpu->isar.id_isar0 = 0x01141110;
cpu->isar.id_isar1 = 0x02111000;
cpu->isar.id_isar2 = 0x21112231;
cpu->isar.id_isar3 = 0x01111110;
cpu->isar.id_isar4 = 0x01310102;
cpu->isar.id_isar5 = 0x00000000;
cpu->isar.id_isar6 = 0x00000000;
}
static void cortex_m3_initfn(Object *obj)