mirror of https://gitee.com/openkylin/qemu.git
Add moxie target code
Signed-off-by: Anthony Green <green@moxielogic.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Anthony Green
Blue Swirl
parent
f7c61bf8fc
commit
525bd324c2
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@ -0,0 +1,2 @@
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obj-y += translate.o helper.o machine.o cpu.o machine.o
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obj-$(CONFIG_SOFTMMU) += mmu.o
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@ -0,0 +1,172 @@
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/*
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* QEMU Moxie CPU
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*
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* Copyright (c) 2013 Anthony Green
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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#include "migration/vmstate.h"
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#include "machine.h"
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static void moxie_cpu_reset(CPUState *s)
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{
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MoxieCPU *cpu = MOXIE_CPU(s);
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MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(cpu);
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CPUMoxieState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(env, 0);
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}
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mcc->parent_reset(s);
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memset(env, 0, offsetof(CPUMoxieState, breakpoints));
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env->pc = 0x1000;
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tlb_flush(env, 1);
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}
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static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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MoxieCPU *cpu = MOXIE_CPU(dev);
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MoxieCPUClass *occ = MOXIE_CPU_GET_CLASS(dev);
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qemu_init_vcpu(&cpu->env);
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cpu_reset(CPU(cpu));
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occ->parent_realize(dev, errp);
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}
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static void moxie_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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MoxieCPU *cpu = MOXIE_CPU(obj);
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static int inited;
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cs->env_ptr = &cpu->env;
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cpu_exec_init(&cpu->env);
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if (tcg_enabled() && !inited) {
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inited = 1;
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moxie_translate_init();
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}
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}
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static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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if (cpu_model == NULL) {
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return NULL;
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}
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oc = object_class_by_name(cpu_model);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_MOXIE_CPU) ||
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object_class_is_abstract(oc))) {
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return NULL;
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}
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return oc;
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}
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static void moxie_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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MoxieCPUClass *mcc = MOXIE_CPU_CLASS(oc);
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mcc->parent_realize = dc->realize;
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dc->realize = moxie_cpu_realizefn;
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mcc->parent_reset = cc->reset;
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cc->reset = moxie_cpu_reset;
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cc->class_by_name = moxie_cpu_class_by_name;
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dc->vmsd = &vmstate_moxie_cpu;
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}
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static void moxielite_initfn(Object *obj)
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{
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/* Set cpu feature flags */
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}
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static void moxie_any_initfn(Object *obj)
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{
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/* Set cpu feature flags */
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}
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typedef struct MoxieCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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} MoxieCPUInfo;
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static const MoxieCPUInfo moxie_cpus[] = {
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{ .name = "MoxieLite", .initfn = moxielite_initfn },
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{ .name = "any", .initfn = moxie_any_initfn },
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};
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MoxieCPU *cpu_moxie_init(const char *cpu_model)
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{
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MoxieCPU *cpu;
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ObjectClass *oc;
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oc = moxie_cpu_class_by_name(cpu_model);
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if (oc == NULL) {
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return NULL;
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}
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cpu = MOXIE_CPU(object_new(object_class_get_name(oc)));
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cpu->env.cpu_model_str = cpu_model;
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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return cpu;
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}
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static void cpu_register(const MoxieCPUInfo *info)
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{
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TypeInfo type_info = {
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.parent = TYPE_MOXIE_CPU,
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.instance_size = sizeof(MoxieCPU),
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.instance_init = info->initfn,
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.class_size = sizeof(MoxieCPUClass),
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};
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type_info.name = g_strdup_printf("%s-" TYPE_MOXIE_CPU, info->name);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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static const TypeInfo moxie_cpu_type_info = {
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.name = TYPE_MOXIE_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(MoxieCPU),
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.instance_init = moxie_cpu_initfn,
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.class_size = sizeof(MoxieCPUClass),
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.class_init = moxie_cpu_class_init,
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};
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static void moxie_cpu_register_types(void)
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{
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int i;
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type_register_static(&moxie_cpu_type_info);
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for (i = 0; i < ARRAY_SIZE(moxie_cpus); i++) {
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cpu_register(&moxie_cpus[i]);
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}
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}
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type_init(moxie_cpu_register_types)
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@ -0,0 +1,167 @@
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/*
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* Moxie emulation
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*
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* Copyright (c) 2008, 2010, 2013 Anthony Green
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _CPU_MOXIE_H
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#define _CPU_MOXIE_H
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#include "config.h"
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#include "qemu-common.h"
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#define TARGET_LONG_BITS 32
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#define CPUArchState struct CPUMoxieState
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#define TARGET_HAS_ICE 1
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#define CPU_SAVE_VERSION 1
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#define ELF_MACHINE 0xFEED /* EM_MOXIE */
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#define MOXIE_EX_DIV0 0
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#define MOXIE_EX_BAD 1
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#define MOXIE_EX_IRQ 2
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#define MOXIE_EX_SWI 3
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#define MOXIE_EX_MMU_MISS 4
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#define MOXIE_EX_BREAK 16
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat.h"
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#define TARGET_PAGE_BITS 12 /* 4k */
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define NB_MMU_MODES 1
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typedef struct CPUMoxieState {
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uint32_t flags; /* general execution flags */
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uint32_t gregs[16]; /* general registers */
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uint32_t sregs[256]; /* special registers */
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uint32_t pc; /* program counter */
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/* Instead of saving the cc value, we save the cmp arguments
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and compute cc on demand. */
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uint32_t cc_a; /* reg a for condition code calculation */
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uint32_t cc_b; /* reg b for condition code calculation */
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void *irq[8];
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CPU_COMMON
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} CPUMoxieState;
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#include "qom/cpu.h"
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#define TYPE_MOXIE_CPU "moxie-cpu"
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#define MOXIE_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(MoxieCPUClass, (klass), TYPE_MOXIE_CPU)
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#define MOXIE_CPU(obj) \
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OBJECT_CHECK(MoxieCPU, (obj), TYPE_MOXIE_CPU)
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#define MOXIE_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(MoxieCPUClass, (obj), TYPE_MOXIE_CPU)
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/**
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* MoxieCPUClass:
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* @parent_reset: The parent class' reset handler.
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*
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* A Moxie CPU model.
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*/
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typedef struct MoxieCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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} MoxieCPUClass;
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/**
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* MoxieCPU:
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* @env: #CPUMoxieState
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*
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* A Moxie CPU.
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*/
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typedef struct MoxieCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUMoxieState env;
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} MoxieCPU;
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static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
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{
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return MOXIE_CPU(container_of(env, MoxieCPU, env));
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}
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#define ENV_GET_CPU(e) CPU(moxie_env_get_cpu(e))
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#define ENV_OFFSET offsetof(MoxieCPU, env)
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MoxieCPU *cpu_moxie_init(const char *cpu_model);
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int cpu_moxie_exec(CPUMoxieState *s);
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void do_interrupt(CPUMoxieState *env);
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void moxie_translate_init(void);
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int cpu_moxie_signal_handler(int host_signum, void *pinfo,
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void *puc);
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static inline CPUMoxieState *cpu_init(const char *cpu_model)
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{
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MoxieCPU *cpu = cpu_moxie_init(cpu_model);
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if (cpu == NULL) {
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return NULL;
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}
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return &cpu->env;
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}
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#define cpu_exec cpu_moxie_exec
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#define cpu_gen_code cpu_moxie_gen_code
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#define cpu_signal_handler cpu_moxie_signal_handler
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static inline int cpu_mmu_index(CPUMoxieState *env)
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{
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return 0;
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}
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#include "exec/cpu-all.h"
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#include "exec/exec-all.h"
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static inline void cpu_pc_from_tb(CPUMoxieState *env, TranslationBlock *tb)
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{
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env->pc = tb->pc;
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}
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static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = 0;
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}
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static inline int cpu_has_work(CPUState *cpu)
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{
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return cpu->interrupt_request & CPU_INTERRUPT_HARD;
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}
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int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
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int rw, int mmu_idx);
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#endif /* _CPU_MOXIE_H */
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@ -0,0 +1,171 @@
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/*
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* Moxie helper routines.
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*
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* Copyright (c) 2008, 2009, 2010, 2013 Anthony Green
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
|
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* License as published by the Free Software Foundation; either
|
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* version 2 of the License, or (at your option) any later version.
|
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*
|
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* This library is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
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* Lesser General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include "config.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "exec/exec-all.h"
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#include "qemu/host-utils.h"
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#include "helper.h"
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#define MMUSUFFIX _mmu
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#define SHIFT 0
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#include "exec/softmmu_template.h"
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#define SHIFT 1
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#include "exec/softmmu_template.h"
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#define SHIFT 2
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#include "exec/softmmu_template.h"
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#define SHIFT 3
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#include "exec/softmmu_template.h"
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/* Try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr)
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{
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int ret;
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ret = cpu_moxie_handle_mmu_fault(env, addr, is_write, mmu_idx);
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if (unlikely(ret)) {
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if (retaddr) {
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cpu_restore_state(env, retaddr);
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}
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}
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cpu_loop_exit(env);
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}
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void helper_raise_exception(CPUMoxieState *env, int ex)
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{
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env->exception_index = ex;
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/* Stash the exception type. */
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env->sregs[2] = ex;
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/* Stash the address where the exception occurred. */
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cpu_restore_state(env, GETPC());
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env->sregs[5] = env->pc;
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/* Jump the the exception handline routine. */
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env->pc = env->sregs[1];
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cpu_loop_exit(env);
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}
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uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b)
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{
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if (unlikely(b == 0)) {
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helper_raise_exception(env, MOXIE_EX_DIV0);
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return 0;
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}
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if (unlikely(a == INT_MIN && b == -1)) {
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return INT_MIN;
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}
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return (int32_t)a / (int32_t)b;
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}
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uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b)
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{
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if (unlikely(b == 0)) {
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helper_raise_exception(env, MOXIE_EX_DIV0);
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return 0;
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}
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return a / b;
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}
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void helper_debug(CPUMoxieState *env)
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{
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env->exception_index = EXCP_DEBUG;
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cpu_loop_exit(env);
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}
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt(CPUState *env)
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{
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env->exception_index = -1;
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}
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int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
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int rw, int mmu_idx)
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{
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env->exception_index = 0xaa;
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env->debug1 = address;
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cpu_dump_state(env, stderr, fprintf, 0);
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return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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return addr;
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}
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#else /* !CONFIG_USER_ONLY */
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int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
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int rw, int mmu_idx)
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{
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MoxieMMUResult res;
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int prot, miss;
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target_ulong phy;
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int r = 1;
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address &= TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx);
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if (miss) {
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/* handle the miss. */
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phy = 0;
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env->exception_index = MOXIE_EX_MMU_MISS;
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} else {
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phy = res.phy;
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r = 0;
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}
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tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
||||
void do_interrupt(CPUMoxieState *env)
|
||||
{
|
||||
switch (env->exception_index) {
|
||||
case MOXIE_EX_BREAK:
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
hwaddr cpu_get_phys_page_debug(CPUMoxieState *env, target_ulong addr)
|
||||
{
|
||||
uint32_t phy = addr;
|
||||
MoxieMMUResult res;
|
||||
int miss;
|
||||
miss = moxie_mmu_translate(&res, env, addr, 0, 0);
|
||||
if (!miss) {
|
||||
phy = res.phy;
|
||||
}
|
||||
return phy;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#include "exec/def-helper.h"
|
||||
|
||||
DEF_HELPER_2(raise_exception, void, env, int)
|
||||
DEF_HELPER_1(debug, void, env)
|
||||
|
||||
DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_WG, i32, env, i32, i32)
|
||||
|
||||
#include "exec/def-helper.h"
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
#include "hw/hw.h"
|
||||
#include "hw/boards.h"
|
||||
|
||||
const VMStateDescription vmstate_moxie_cpu = {
|
||||
.name = "cpu",
|
||||
.version_id = CPU_SAVE_VERSION,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(flags, CPUMoxieState),
|
||||
VMSTATE_UINT32_ARRAY(gregs, CPUMoxieState, 16),
|
||||
VMSTATE_UINT32_ARRAY(sregs, CPUMoxieState, 256),
|
||||
VMSTATE_UINT32(pc, CPUMoxieState),
|
||||
VMSTATE_UINT32(cc_a, CPUMoxieState),
|
||||
VMSTATE_UINT32(cc_b, CPUMoxieState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
void cpu_save(QEMUFile *f, void *opaque)
|
||||
{
|
||||
vmstate_save_state(f, &vmstate_moxie_cpu, opaque);
|
||||
}
|
||||
|
||||
int cpu_load(QEMUFile *f, void *opaque, int version_id)
|
||||
{
|
||||
return vmstate_load_state(f, &vmstate_moxie_cpu, opaque, version_id);
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
extern const VMStateDescription vmstate_moxie_cpu;
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Moxie mmu emulation.
|
||||
*
|
||||
* Copyright (c) 2008, 2013 Anthony Green
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "config.h"
|
||||
#include "cpu.h"
|
||||
#include "mmu.h"
|
||||
#include "exec/exec-all.h"
|
||||
|
||||
int moxie_mmu_translate(MoxieMMUResult *res,
|
||||
CPUMoxieState *env, uint32_t vaddr,
|
||||
int rw, int mmu_idx)
|
||||
{
|
||||
/* Perform no translation yet. */
|
||||
res->phy = vaddr;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
#define MOXIE_MMU_ERR_EXEC 0
|
||||
#define MOXIE_MMU_ERR_READ 1
|
||||
#define MOXIE_MMU_ERR_WRITE 2
|
||||
#define MOXIE_MMU_ERR_FLUSH 3
|
||||
|
||||
typedef struct {
|
||||
uint32_t phy;
|
||||
uint32_t pfn;
|
||||
int g:1;
|
||||
int v:1;
|
||||
int k:1;
|
||||
int w:1;
|
||||
int e:1;
|
||||
int cause_op;
|
||||
} MoxieMMUResult;
|
||||
|
||||
int moxie_mmu_translate(MoxieMMUResult *res,
|
||||
CPUMoxieState *env, uint32_t vaddr,
|
||||
int rw, int mmu_idx);
|
||||
|
|
@ -0,0 +1,926 @@
|
|||
/*
|
||||
* Moxie emulation for qemu: main translation routines.
|
||||
*
|
||||
* Copyright (c) 2009, 2013 Anthony Green
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public License
|
||||
* as published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* For information on the Moxie architecture, see
|
||||
* http://moxielogic.org/wiki
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <inttypes.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include "cpu.h"
|
||||
#include "exec/exec-all.h"
|
||||
#include "disas/disas.h"
|
||||
#include "tcg-op.h"
|
||||
|
||||
#include "helper.h"
|
||||
#define GEN_HELPER 1
|
||||
#include "helper.h"
|
||||
|
||||
/* This is the state at translation time. */
|
||||
typedef struct DisasContext {
|
||||
struct TranslationBlock *tb;
|
||||
target_ulong pc, saved_pc;
|
||||
uint32_t opcode;
|
||||
uint32_t fp_status;
|
||||
/* Routine used to access memory */
|
||||
int memidx;
|
||||
int bstate;
|
||||
target_ulong btarget;
|
||||
int singlestep_enabled;
|
||||
} DisasContext;
|
||||
|
||||
enum {
|
||||
BS_NONE = 0, /* We go out of the TB without reaching a branch or an
|
||||
* exception condition */
|
||||
BS_STOP = 1, /* We want to stop translation for any reason */
|
||||
BS_BRANCH = 2, /* We reached a branch condition */
|
||||
BS_EXCP = 3, /* We reached an exception condition */
|
||||
};
|
||||
|
||||
static TCGv cpu_pc;
|
||||
static TCGv cpu_gregs[16];
|
||||
static TCGv_ptr cpu_env;
|
||||
static TCGv cc_a, cc_b;
|
||||
|
||||
#include "exec/gen-icount.h"
|
||||
|
||||
#define REG(x) (cpu_gregs[x])
|
||||
|
||||
/* Extract the signed 10-bit offset from a 16-bit branch
|
||||
instruction. */
|
||||
static int extract_branch_offset(int opcode)
|
||||
{
|
||||
return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
|
||||
}
|
||||
|
||||
void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf,
|
||||
int flags)
|
||||
{
|
||||
int i;
|
||||
cpu_fprintf(f, "pc=0x%08x\n", env->pc);
|
||||
cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
|
||||
env->gregs[0], env->gregs[1], env->gregs[2], env->gregs[3]);
|
||||
for (i = 4; i < 16; i += 4) {
|
||||
cpu_fprintf(f, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
|
||||
i-2, env->gregs[i], i-1, env->gregs[i + 1],
|
||||
i, env->gregs[i + 2], i+1, env->gregs[i + 3]);
|
||||
}
|
||||
for (i = 4; i < 16; i += 4) {
|
||||
cpu_fprintf(f, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
|
||||
i-2, env->sregs[i], i-1, env->sregs[i + 1],
|
||||
i, env->sregs[i + 2], i+1, env->sregs[i + 3]);
|
||||
}
|
||||
}
|
||||
|
||||
void moxie_translate_init(void)
|
||||
{
|
||||
int i;
|
||||
static int done_init;
|
||||
static const char * const gregnames[16] = {
|
||||
"$fp", "$sp", "$r0", "$r1",
|
||||
"$r2", "$r3", "$r4", "$r5",
|
||||
"$r6", "$r7", "$r8", "$r9",
|
||||
"$r10", "$r11", "$r12", "$r13"
|
||||
};
|
||||
|
||||
if (done_init) {
|
||||
return;
|
||||
}
|
||||
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
||||
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUMoxieState, pc), "$pc");
|
||||
for (i = 0; i < 16; i++)
|
||||
cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUMoxieState, gregs[i]),
|
||||
gregnames[i]);
|
||||
|
||||
cc_a = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUMoxieState, cc_a), "cc_a");
|
||||
cc_b = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUMoxieState, cc_b), "cc_b");
|
||||
|
||||
done_init = 1;
|
||||
}
|
||||
|
||||
static inline void gen_goto_tb(CPUMoxieState *env, DisasContext *ctx,
|
||||
int n, target_ulong dest)
|
||||
{
|
||||
TranslationBlock *tb;
|
||||
tb = ctx->tb;
|
||||
|
||||
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
||||
!ctx->singlestep_enabled) {
|
||||
tcg_gen_goto_tb(n);
|
||||
tcg_gen_movi_i32(cpu_pc, dest);
|
||||
tcg_gen_exit_tb((long) tb + n);
|
||||
} else {
|
||||
tcg_gen_movi_i32(cpu_pc, dest);
|
||||
if (ctx->singlestep_enabled) {
|
||||
gen_helper_debug(cpu_env);
|
||||
}
|
||||
tcg_gen_exit_tb(0);
|
||||
}
|
||||
}
|
||||
|
||||
static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
|
||||
{
|
||||
CPUMoxieState *env = &cpu->env;
|
||||
|
||||
/* Local cache for the instruction opcode. */
|
||||
int opcode;
|
||||
/* Set the default instruction length. */
|
||||
int length = 2;
|
||||
|
||||
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
||||
tcg_gen_debug_insn_start(ctx->pc);
|
||||
}
|
||||
|
||||
/* Examine the 16-bit opcode. */
|
||||
opcode = ctx->opcode;
|
||||
|
||||
/* Decode instruction. */
|
||||
if (opcode & (1 << 15)) {
|
||||
if (opcode & (1 << 14)) {
|
||||
/* This is a Form 3 instruction. */
|
||||
int inst = (opcode >> 10 & 0xf);
|
||||
|
||||
#define BRANCH(cond) \
|
||||
do { \
|
||||
int l1 = gen_new_label(); \
|
||||
tcg_gen_brcond_i32(cond, cc_a, cc_b, l1); \
|
||||
gen_goto_tb(env, ctx, 1, ctx->pc+2); \
|
||||
gen_set_label(l1); \
|
||||
gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
|
||||
ctx->bstate = BS_BRANCH; \
|
||||
} while (0)
|
||||
|
||||
switch (inst) {
|
||||
case 0x00: /* beq */
|
||||
BRANCH(TCG_COND_EQ);
|
||||
break;
|
||||
case 0x01: /* bne */
|
||||
BRANCH(TCG_COND_NE);
|
||||
break;
|
||||
case 0x02: /* blt */
|
||||
BRANCH(TCG_COND_LT);
|
||||
break;
|
||||
case 0x03: /* bgt */
|
||||
BRANCH(TCG_COND_GT);
|
||||
break;
|
||||
case 0x04: /* bltu */
|
||||
BRANCH(TCG_COND_LTU);
|
||||
break;
|
||||
case 0x05: /* bgtu */
|
||||
BRANCH(TCG_COND_GTU);
|
||||
break;
|
||||
case 0x06: /* bge */
|
||||
BRANCH(TCG_COND_GE);
|
||||
break;
|
||||
case 0x07: /* ble */
|
||||
BRANCH(TCG_COND_LE);
|
||||
break;
|
||||
case 0x08: /* bgeu */
|
||||
BRANCH(TCG_COND_GEU);
|
||||
break;
|
||||
case 0x09: /* bleu */
|
||||
BRANCH(TCG_COND_LEU);
|
||||
break;
|
||||
default:
|
||||
{
|
||||
TCGv temp = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
|
||||
gen_helper_raise_exception(cpu_env, temp);
|
||||
tcg_temp_free_i32(temp);
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* This is a Form 2 instruction. */
|
||||
int inst = (opcode >> 12 & 0x3);
|
||||
switch (inst) {
|
||||
case 0x00: /* inc */
|
||||
{
|
||||
int a = (opcode >> 8) & 0xf;
|
||||
unsigned int v = (opcode & 0xff);
|
||||
tcg_gen_addi_i32(REG(a), REG(a), v);
|
||||
}
|
||||
break;
|
||||
case 0x01: /* dec */
|
||||
{
|
||||
int a = (opcode >> 8) & 0xf;
|
||||
unsigned int v = (opcode & 0xff);
|
||||
tcg_gen_subi_i32(REG(a), REG(a), v);
|
||||
}
|
||||
break;
|
||||
case 0x02: /* gsr */
|
||||
{
|
||||
int a = (opcode >> 8) & 0xf;
|
||||
unsigned v = (opcode & 0xff);
|
||||
tcg_gen_ld_i32(REG(a), cpu_env,
|
||||
offsetof(CPUMoxieState, sregs[v]));
|
||||
}
|
||||
break;
|
||||
case 0x03: /* ssr */
|
||||
{
|
||||
int a = (opcode >> 8) & 0xf;
|
||||
unsigned v = (opcode & 0xff);
|
||||
tcg_gen_st_i32(REG(a), cpu_env,
|
||||
offsetof(CPUMoxieState, sregs[v]));
|
||||
}
|
||||
break;
|
||||
default:
|
||||
{
|
||||
TCGv temp = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
|
||||
gen_helper_raise_exception(cpu_env, temp);
|
||||
tcg_temp_free_i32(temp);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* This is a Form 1 instruction. */
|
||||
int inst = opcode >> 8;
|
||||
switch (inst) {
|
||||
case 0x00: /* nop */
|
||||
break;
|
||||
case 0x01: /* ldi.l (immediate) */
|
||||
{
|
||||
int reg = (opcode >> 4) & 0xf;
|
||||
int val = cpu_ldl_code(env, ctx->pc+2);
|
||||
tcg_gen_movi_i32(REG(reg), val);
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x02: /* mov (register-to-register) */
|
||||
{
|
||||
int dest = (opcode >> 4) & 0xf;
|
||||
int src = opcode & 0xf;
|
||||
tcg_gen_mov_i32(REG(dest), REG(src));
|
||||
}
|
||||
break;
|
||||
case 0x03: /* jsra */
|
||||
{
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_movi_i32(t1, ctx->pc + 6);
|
||||
|
||||
/* Make space for the static chain and return address. */
|
||||
tcg_gen_subi_i32(t2, REG(1), 8);
|
||||
tcg_gen_mov_i32(REG(1), t2);
|
||||
tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
|
||||
|
||||
/* Push the current frame pointer. */
|
||||
tcg_gen_subi_i32(t2, REG(1), 4);
|
||||
tcg_gen_mov_i32(REG(1), t2);
|
||||
tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
|
||||
|
||||
/* Set the pc and $fp. */
|
||||
tcg_gen_mov_i32(REG(0), REG(1));
|
||||
|
||||
gen_goto_tb(env, ctx, 0, cpu_ldl_code(env, ctx->pc+2));
|
||||
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
ctx->bstate = BS_BRANCH;
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x04: /* ret */
|
||||
{
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
|
||||
/* The new $sp is the old $fp. */
|
||||
tcg_gen_mov_i32(REG(1), REG(0));
|
||||
|
||||
/* Pop the frame pointer. */
|
||||
tcg_gen_qemu_ld32u(REG(0), REG(1), ctx->memidx);
|
||||
tcg_gen_addi_i32(t1, REG(1), 4);
|
||||
tcg_gen_mov_i32(REG(1), t1);
|
||||
|
||||
|
||||
/* Pop the return address and skip over the static chain
|
||||
slot. */
|
||||
tcg_gen_qemu_ld32u(cpu_pc, REG(1), ctx->memidx);
|
||||
tcg_gen_addi_i32(t1, REG(1), 8);
|
||||
tcg_gen_mov_i32(REG(1), t1);
|
||||
|
||||
tcg_temp_free_i32(t1);
|
||||
|
||||
/* Jump... */
|
||||
tcg_gen_exit_tb(0);
|
||||
|
||||
ctx->bstate = BS_BRANCH;
|
||||
}
|
||||
break;
|
||||
case 0x05: /* add.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_add_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x06: /* push */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
tcg_gen_subi_i32(t1, REG(a), 4);
|
||||
tcg_gen_mov_i32(REG(a), t1);
|
||||
tcg_gen_qemu_st32(REG(b), REG(a), ctx->memidx);
|
||||
tcg_temp_free_i32(t1);
|
||||
}
|
||||
break;
|
||||
case 0x07: /* pop */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_qemu_ld32u(REG(b), REG(a), ctx->memidx);
|
||||
tcg_gen_addi_i32(t1, REG(a), 4);
|
||||
tcg_gen_mov_i32(REG(a), t1);
|
||||
tcg_temp_free_i32(t1);
|
||||
}
|
||||
break;
|
||||
case 0x08: /* lda.l */
|
||||
{
|
||||
int reg = (opcode >> 4) & 0xf;
|
||||
|
||||
TCGv ptr = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_ld32u(REG(reg), ptr, ctx->memidx);
|
||||
tcg_temp_free_i32(ptr);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x09: /* sta.l */
|
||||
{
|
||||
int val = (opcode >> 4) & 0xf;
|
||||
|
||||
TCGv ptr = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_st32(REG(val), ptr, ctx->memidx);
|
||||
tcg_temp_free_i32(ptr);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x0a: /* ld.l (register indirect) */
|
||||
{
|
||||
int src = opcode & 0xf;
|
||||
int dest = (opcode >> 4) & 0xf;
|
||||
|
||||
tcg_gen_qemu_ld32u(REG(dest), REG(src), ctx->memidx);
|
||||
}
|
||||
break;
|
||||
case 0x0b: /* st.l */
|
||||
{
|
||||
int dest = (opcode >> 4) & 0xf;
|
||||
int val = opcode & 0xf;
|
||||
|
||||
tcg_gen_qemu_st32(REG(val), REG(dest), ctx->memidx);
|
||||
}
|
||||
break;
|
||||
case 0x0c: /* ldo.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_ld32u(t2, t1, ctx->memidx);
|
||||
tcg_gen_mov_i32(REG(a), t2);
|
||||
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x0d: /* sto.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_st32(REG(b), t1, ctx->memidx);
|
||||
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x0e: /* cmp */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_mov_i32(cc_a, REG(a));
|
||||
tcg_gen_mov_i32(cc_b, REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x19: /* jsr */
|
||||
{
|
||||
int fnreg = (opcode >> 4) & 0xf;
|
||||
|
||||
/* Load the stack pointer into T0. */
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_movi_i32(t1, ctx->pc+2);
|
||||
|
||||
/* Make space for the static chain and return address. */
|
||||
tcg_gen_subi_i32(t2, REG(1), 8);
|
||||
tcg_gen_mov_i32(REG(1), t2);
|
||||
tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
|
||||
|
||||
/* Push the current frame pointer. */
|
||||
tcg_gen_subi_i32(t2, REG(1), 4);
|
||||
tcg_gen_mov_i32(REG(1), t2);
|
||||
tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
|
||||
|
||||
/* Set the pc and $fp. */
|
||||
tcg_gen_mov_i32(REG(0), REG(1));
|
||||
tcg_gen_mov_i32(cpu_pc, REG(fnreg));
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
tcg_gen_exit_tb(0);
|
||||
ctx->bstate = BS_BRANCH;
|
||||
}
|
||||
break;
|
||||
case 0x1a: /* jmpa */
|
||||
{
|
||||
tcg_gen_movi_i32(cpu_pc, cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_exit_tb(0);
|
||||
ctx->bstate = BS_BRANCH;
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x1b: /* ldi.b (immediate) */
|
||||
{
|
||||
int reg = (opcode >> 4) & 0xf;
|
||||
int val = cpu_ldl_code(env, ctx->pc+2);
|
||||
tcg_gen_movi_i32(REG(reg), val);
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x1c: /* ld.b (register indirect) */
|
||||
{
|
||||
int src = opcode & 0xf;
|
||||
int dest = (opcode >> 4) & 0xf;
|
||||
|
||||
tcg_gen_qemu_ld8u(REG(dest), REG(src), ctx->memidx);
|
||||
}
|
||||
break;
|
||||
case 0x1d: /* lda.b */
|
||||
{
|
||||
int reg = (opcode >> 4) & 0xf;
|
||||
|
||||
TCGv ptr = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_ld8u(REG(reg), ptr, ctx->memidx);
|
||||
tcg_temp_free_i32(ptr);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x1e: /* st.b */
|
||||
{
|
||||
int dest = (opcode >> 4) & 0xf;
|
||||
int val = opcode & 0xf;
|
||||
|
||||
tcg_gen_qemu_st8(REG(val), REG(dest), ctx->memidx);
|
||||
}
|
||||
break;
|
||||
case 0x1f: /* sta.b */
|
||||
{
|
||||
int val = (opcode >> 4) & 0xf;
|
||||
|
||||
TCGv ptr = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_st8(REG(val), ptr, ctx->memidx);
|
||||
tcg_temp_free_i32(ptr);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x20: /* ldi.s (immediate) */
|
||||
{
|
||||
int reg = (opcode >> 4) & 0xf;
|
||||
int val = cpu_ldl_code(env, ctx->pc+2);
|
||||
tcg_gen_movi_i32(REG(reg), val);
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x21: /* ld.s (register indirect) */
|
||||
{
|
||||
int src = opcode & 0xf;
|
||||
int dest = (opcode >> 4) & 0xf;
|
||||
|
||||
tcg_gen_qemu_ld16u(REG(dest), REG(src), ctx->memidx);
|
||||
}
|
||||
break;
|
||||
case 0x22: /* lda.s */
|
||||
{
|
||||
int reg = (opcode >> 4) & 0xf;
|
||||
|
||||
TCGv ptr = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_ld16u(REG(reg), ptr, ctx->memidx);
|
||||
tcg_temp_free_i32(ptr);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x23: /* st.s */
|
||||
{
|
||||
int dest = (opcode >> 4) & 0xf;
|
||||
int val = opcode & 0xf;
|
||||
|
||||
tcg_gen_qemu_st16(REG(val), REG(dest), ctx->memidx);
|
||||
}
|
||||
break;
|
||||
case 0x24: /* sta.s */
|
||||
{
|
||||
int val = (opcode >> 4) & 0xf;
|
||||
|
||||
TCGv ptr = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_st16(REG(val), ptr, ctx->memidx);
|
||||
tcg_temp_free_i32(ptr);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x25: /* jmp */
|
||||
{
|
||||
int reg = (opcode >> 4) & 0xf;
|
||||
tcg_gen_mov_i32(cpu_pc, REG(reg));
|
||||
tcg_gen_exit_tb(0);
|
||||
ctx->bstate = BS_BRANCH;
|
||||
}
|
||||
break;
|
||||
case 0x26: /* and */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_and_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x27: /* lshr */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv sv = tcg_temp_new_i32();
|
||||
tcg_gen_andi_i32(sv, REG(b), 0x1f);
|
||||
tcg_gen_shr_i32(REG(a), REG(a), sv);
|
||||
tcg_temp_free_i32(sv);
|
||||
}
|
||||
break;
|
||||
case 0x28: /* ashl */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv sv = tcg_temp_new_i32();
|
||||
tcg_gen_andi_i32(sv, REG(b), 0x1f);
|
||||
tcg_gen_shl_i32(REG(a), REG(a), sv);
|
||||
tcg_temp_free_i32(sv);
|
||||
}
|
||||
break;
|
||||
case 0x29: /* sub.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_sub_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x2a: /* neg */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_neg_i32(REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x2b: /* or */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_or_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x2c: /* not */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_not_i32(REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x2d: /* ashr */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv sv = tcg_temp_new_i32();
|
||||
tcg_gen_andi_i32(sv, REG(b), 0x1f);
|
||||
tcg_gen_sar_i32(REG(a), REG(a), sv);
|
||||
tcg_temp_free_i32(sv);
|
||||
}
|
||||
break;
|
||||
case 0x2e: /* xor */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_xor_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x2f: /* mul.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
tcg_gen_mul_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x30: /* swi */
|
||||
{
|
||||
int val = cpu_ldl_code(env, ctx->pc+2);
|
||||
|
||||
TCGv temp = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(temp, val);
|
||||
tcg_gen_st_i32(temp, cpu_env,
|
||||
offsetof(CPUMoxieState, sregs[3]));
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
tcg_gen_movi_i32(temp, MOXIE_EX_SWI);
|
||||
gen_helper_raise_exception(cpu_env, temp);
|
||||
tcg_temp_free_i32(temp);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x31: /* div.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
gen_helper_div(REG(a), cpu_env, REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x32: /* udiv.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
gen_helper_udiv(REG(a), cpu_env, REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x33: /* mod.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
tcg_gen_rem_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x34: /* umod.l */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
tcg_gen_remu_i32(REG(a), REG(a), REG(b));
|
||||
}
|
||||
break;
|
||||
case 0x35: /* brk */
|
||||
{
|
||||
TCGv temp = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
tcg_gen_movi_i32(temp, MOXIE_EX_BREAK);
|
||||
gen_helper_raise_exception(cpu_env, temp);
|
||||
tcg_temp_free_i32(temp);
|
||||
}
|
||||
break;
|
||||
case 0x36: /* ldo.b */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_ld8u(t2, t1, ctx->memidx);
|
||||
tcg_gen_mov_i32(REG(a), t2);
|
||||
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x37: /* sto.b */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_st8(REG(b), t1, ctx->memidx);
|
||||
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x38: /* ldo.s */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_ld16u(t2, t1, ctx->memidx);
|
||||
tcg_gen_mov_i32(REG(a), t2);
|
||||
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
case 0x39: /* sto.s */
|
||||
{
|
||||
int a = (opcode >> 4) & 0xf;
|
||||
int b = opcode & 0xf;
|
||||
|
||||
TCGv t1 = tcg_temp_new_i32();
|
||||
TCGv t2 = tcg_temp_new_i32();
|
||||
tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
|
||||
tcg_gen_qemu_st16(REG(b), t1, ctx->memidx);
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
length = 6;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
{
|
||||
TCGv temp = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
|
||||
gen_helper_raise_exception(cpu_env, temp);
|
||||
tcg_temp_free_i32(temp);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
/* generate intermediate code for basic block 'tb'. */
|
||||
static void
|
||||
gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
|
||||
bool search_pc)
|
||||
{
|
||||
DisasContext ctx;
|
||||
target_ulong pc_start;
|
||||
uint16_t *gen_opc_end;
|
||||
CPUBreakpoint *bp;
|
||||
int j, lj = -1;
|
||||
CPUMoxieState *env = &cpu->env;
|
||||
int num_insns;
|
||||
|
||||
pc_start = tb->pc;
|
||||
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
||||
ctx.pc = pc_start;
|
||||
ctx.saved_pc = -1;
|
||||
ctx.tb = tb;
|
||||
ctx.memidx = 0;
|
||||
ctx.singlestep_enabled = 0;
|
||||
ctx.bstate = BS_NONE;
|
||||
num_insns = 0;
|
||||
|
||||
gen_tb_start();
|
||||
do {
|
||||
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
||||
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
||||
if (ctx.pc == bp->pc) {
|
||||
tcg_gen_movi_i32(cpu_pc, ctx.pc);
|
||||
gen_helper_debug(cpu_env);
|
||||
ctx.bstate = BS_EXCP;
|
||||
goto done_generating;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (search_pc) {
|
||||
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
|
||||
if (lj < j) {
|
||||
lj++;
|
||||
while (lj < j) {
|
||||
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
||||
}
|
||||
}
|
||||
tcg_ctx.gen_opc_pc[lj] = ctx.pc;
|
||||
tcg_ctx.gen_opc_instr_start[lj] = 1;
|
||||
tcg_ctx.gen_opc_icount[lj] = num_insns;
|
||||
}
|
||||
ctx.opcode = cpu_lduw_code(env, ctx.pc);
|
||||
ctx.pc += decode_opc(cpu, &ctx);
|
||||
num_insns++;
|
||||
|
||||
if (env->singlestep_enabled) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
|
||||
break;
|
||||
}
|
||||
} while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);
|
||||
|
||||
if (env->singlestep_enabled) {
|
||||
tcg_gen_movi_tl(cpu_pc, ctx.pc);
|
||||
gen_helper_debug(cpu_env);
|
||||
} else {
|
||||
switch (ctx.bstate) {
|
||||
case BS_STOP:
|
||||
case BS_NONE:
|
||||
gen_goto_tb(env, &ctx, 0, ctx.pc);
|
||||
break;
|
||||
case BS_EXCP:
|
||||
tcg_gen_exit_tb(0);
|
||||
break;
|
||||
case BS_BRANCH:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
done_generating:
|
||||
gen_tb_end(tb, num_insns);
|
||||
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
|
||||
if (search_pc) {
|
||||
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
|
||||
lj++;
|
||||
while (lj <= j) {
|
||||
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
||||
}
|
||||
} else {
|
||||
tb->size = ctx.pc - pc_start;
|
||||
tb->icount = num_insns;
|
||||
}
|
||||
}
|
||||
|
||||
void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
|
||||
{
|
||||
gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, false);
|
||||
}
|
||||
|
||||
void gen_intermediate_code_pc(CPUMoxieState *env, struct TranslationBlock *tb)
|
||||
{
|
||||
gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, true);
|
||||
}
|
||||
|
||||
void restore_state_to_opc(CPUMoxieState *env, TranslationBlock *tb, int pc_pos)
|
||||
{
|
||||
env->pc = tcg_ctx.gen_opc_pc[pc_pos];
|
||||
}
|
||||
Loading…
Reference in New Issue