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target/ppc: fix xxspltw for big endian hosts 

Fix a typo in the host endianness macro and add a simple test to detect
regressions.

Fixes: 9bb0048ec6 ("target/ppc: convert xxspltw to vector operations")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220310172047.61094-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-14 15:57:17 +01:00 committed by Cédric Le Goater
parent c6242335b3
commit 52d324ff13
4 changed files with 49 additions and 1 deletions
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2
target/ppc/translate/vsx-impl.c.inc
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@ -1552,7 +1552,7 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2_uim2 *a)
tofs = vsr_full_offset(a->xt);
bofs = vsr_full_offset(a->xb);
bofs += a->uim << MO_32;
#ifndef HOST_WORDS_BIG_ENDIAN
#ifndef HOST_WORDS_BIGENDIAN
bofs ^= 8 | 4;
#endif

1
tests/tcg/ppc64/Makefile.target
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@ -27,5 +27,6 @@ run-sha512-vector: QEMU_OPTS+=-cpu POWER10
run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
PPC64_TESTS += signal_save_restore_xer
PPC64_TESTS += xxspltw
TESTS += $(PPC64_TESTS)

1
tests/tcg/ppc64le/Makefile.target
View File

@ -25,5 +25,6 @@ run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
PPC64LE_TESTS += mtfsf
PPC64LE_TESTS += signal_save_restore_xer
PPC64LE_TESTS += xxspltw
TESTS += $(PPC64LE_TESTS)

46
tests/tcg/ppc64le/xxspltw.c Normal file
View File

@ -0,0 +1,46 @@
#include <stdio.h>
#include <stdint.h>
#include <inttypes.h>
#include <assert.h>
#define WORD_A 0xAAAAAAAAUL
#define WORD_B 0xBBBBBBBBUL
#define WORD_C 0xCCCCCCCCUL
#define WORD_D 0xDDDDDDDDUL
#define DWORD_HI (WORD_A << 32 | WORD_B)
#define DWORD_LO (WORD_C << 32 | WORD_D)
#define TEST(HI, LO, UIM, RES) \
do { \
union { \
uint64_t u; \
double f; \
} h = { .u = HI }, l = { .u = LO }; \
/* \
* Use a pair of FPRs to load the VSR avoiding insns \
* newer than xxswapd. \
*/ \
asm("xxmrghd 32, %0, %1\n\t" \
"xxspltw 32, 32, %2\n\t" \
"xxmrghd %0, 32, %0\n\t" \
"xxswapd 32, 32\n\t" \
"xxmrghd %1, 32, %1\n\t" \
: "+f" (h.f), "+f" (l.f) \
: "i" (UIM) \
: "v0"); \
printf("xxspltw(0x%016" PRIx64 "%016" PRIx64 ", %d) =" \
" %016" PRIx64 "%016" PRIx64 "\n", HI, LO, UIM, \
h.u, l.u); \
assert(h.u == (RES)); \
assert(l.u == (RES)); \
} while (0)
int main(void)
{
TEST(DWORD_HI, DWORD_LO, 0, WORD_A << 32 | WORD_A);
TEST(DWORD_HI, DWORD_LO, 1, WORD_B << 32 | WORD_B);
TEST(DWORD_HI, DWORD_LO, 2, WORD_C << 32 | WORD_C);
TEST(DWORD_HI, DWORD_LO, 3, WORD_D << 32 | WORD_D);
return 0;
}