Update based on Stuart Brady's comments

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4026 c046a42c-6fe2-441c-8c8c-71466251a162

tcg/sparc/tcg-target.c

@@ -297,7 +297,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
 
     switch (opc) {
     case INDEX_op_exit_tb:
-        tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_O0, args[0]);
+        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_O0, args[0]);
         tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_O7) |
                   INSN_IMM13(8));
         tcg_out_nop(s);
@@ -305,16 +305,15 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     case INDEX_op_goto_tb:
         if (s->tb_jmp_offset) {
             /* direct jump method */
-            tcg_out32(s, CALL | 0);
+            tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_I5, args[0]);
             s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
-            tcg_out_nop(s);
         } else {
             /* indirect jump method */
-            tcg_out_ld_raw(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
-            tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) |
-                      INSN_RS2(TCG_REG_G0));
-            tcg_out_nop(s);
+            tcg_out_ld_raw(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
         }
+        tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
+                  INSN_RS2(TCG_REG_G0));
+        tcg_out_nop(s);
         s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
         break;
     case INDEX_op_call:
@@ -362,7 +361,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         break;
     case INDEX_op_ld_i32:
 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
-    case INDEX_op_ld_i32u_i64:
+    case INDEX_op_ld32u_i64:
 #endif
         tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
         break;
@@ -374,10 +373,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         break;
     case INDEX_op_st_i32:
 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
-    case INDEX_op_st_i32_i64:
+    case INDEX_op_st32_i64:
 #endif
         tcg_out_ldst(s, args[0], args[1], args[2], STW);
         break;
+        OP_32_64(add);
+        c = ARITH_ADD;
+        goto gen_arith32;
         OP_32_64(sub);
         c = ARITH_SUB;
         goto gen_arith32;
@@ -402,16 +404,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     case INDEX_op_mul_i32:
         c = ARITH_UMUL;
         goto gen_arith32;
-        OP_32_64(add);
-        c = ARITH_ADD;
-    gen_arith32:
-        if (const_args[2]) {
-            tcg_out_arithi(s, args[0], args[1], args[2], c);
-        } else {
-            tcg_out_arith(s, args[0], args[1], args[2], c);
-        }
-        break;
-
     case INDEX_op_div2_i32:
 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
         c = ARITH_SDIVX;
@@ -467,6 +459,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     case INDEX_op_movi_i64:
         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
         break;
+    case INDEX_op_ld32s_i64:
+        tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
+        break;
     case INDEX_op_ld_i64:
         tcg_out_ldst(s, args[0], args[1], args[2], LDX);
         break;
@@ -486,7 +481,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         c = ARITH_MULX;
         goto gen_arith32;
     case INDEX_op_div2_i64:
-        c = ARITH_DIVX;
+        c = ARITH_SDIVX;
         goto gen_arith32;
     case INDEX_op_divu2_i64:
         c = ARITH_UDIVX;
@@ -503,6 +498,14 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         break;
 
 #endif
+    gen_arith32:
+        if (const_args[2]) {
+            tcg_out_arithi(s, args[0], args[1], args[2], c);
+        } else {
+            tcg_out_arith(s, args[0], args[1], args[2], c);
+        }
+        break;
+
     default:
         fprintf(stderr, "unknown opcode 0x%x\n", opc);
         tcg_abort();
@@ -511,7 +514,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
 
 static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_exit_tb, { } },
-    { INDEX_op_goto_tb, { } },
+    { INDEX_op_goto_tb, { "r" } },
     { INDEX_op_call, { "ri" } },
     { INDEX_op_jmp, { "ri" } },
     { INDEX_op_br, { } },
@@ -527,18 +530,18 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_st16_i32, { "r", "r" } },
     { INDEX_op_st_i32, { "r", "r" } },
 
-    { INDEX_op_add_i32, { "r", "0", "rJ" } },
-    { INDEX_op_mul_i32, { "r", "0", "rJ" } },
+    { INDEX_op_add_i32, { "r", "r", "rJ" } },
+    { INDEX_op_mul_i32, { "r", "r", "rJ" } },
     { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
     { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
-    { INDEX_op_sub_i32, { "r", "0", "rJ" } },
-    { INDEX_op_and_i32, { "r", "0", "rJ" } },
-    { INDEX_op_or_i32, { "r", "0", "rJ" } },
-    { INDEX_op_xor_i32, { "r", "0", "rJ" } },
+    { INDEX_op_sub_i32, { "r", "r", "rJ" } },
+    { INDEX_op_and_i32, { "r", "r", "rJ" } },
+    { INDEX_op_or_i32, { "r", "r", "rJ" } },
+    { INDEX_op_xor_i32, { "r", "r", "rJ" } },
 
-    { INDEX_op_shl_i32, { "r", "0", "rJ" } },
-    { INDEX_op_shr_i32, { "r", "0", "rJ" } },
-    { INDEX_op_sar_i32, { "r", "0", "rJ" } },
+    { INDEX_op_shl_i32, { "r", "r", "rJ" } },
+    { INDEX_op_shr_i32, { "r", "r", "rJ" } },
+    { INDEX_op_sar_i32, { "r", "r", "rJ" } },
 
     { INDEX_op_brcond_i32, { "r", "ri" } },
 
@@ -568,18 +571,18 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_st32_i64, { "r", "r" } },
     { INDEX_op_st_i64, { "r", "r" } },
 
-    { INDEX_op_add_i64, { "r", "0", "rJ" } },
-    { INDEX_op_mul_i64, { "r", "0", "rJ" } },
+    { INDEX_op_add_i64, { "r", "r", "rJ" } },
+    { INDEX_op_mul_i64, { "r", "r", "rJ" } },
     { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
     { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
-    { INDEX_op_sub_i64, { "r", "0", "rJ" } },
-    { INDEX_op_and_i64, { "r", "0", "rJ" } },
-    { INDEX_op_or_i64, { "r", "0", "rJ" } },
-    { INDEX_op_xor_i64, { "r", "0", "rJ" } },
+    { INDEX_op_sub_i64, { "r", "r", "rJ" } },
+    { INDEX_op_and_i64, { "r", "r", "rJ" } },
+    { INDEX_op_or_i64, { "r", "r", "rJ" } },
+    { INDEX_op_xor_i64, { "r", "r", "rJ" } },
 
-    { INDEX_op_shl_i64, { "r", "0", "rJ" } },
-    { INDEX_op_shr_i64, { "r", "0", "rJ" } },
-    { INDEX_op_sar_i64, { "r", "0", "rJ" } },
+    { INDEX_op_shl_i64, { "r", "r", "rJ" } },
+    { INDEX_op_shr_i64, { "r", "r", "rJ" } },
+    { INDEX_op_sar_i64, { "r", "r", "rJ" } },
 
     { INDEX_op_brcond_i64, { "r", "ri" } },
 #endif
@@ -604,6 +607,7 @@ void tcg_target_init(TCGContext *s)
 
     tcg_regset_clear(s->reserved_regs);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);