mirror of https://gitee.com/openkylin/qemu.git
ETRAX: Allow boot from flash. Support the watchdog timer and resets through it.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4592 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
2ea815cac7
commit
5439779e84
110
hw/etraxfs.c
110
hw/etraxfs.c
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@ -32,25 +32,29 @@
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#include "etraxfs_dma.h"
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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}
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/* Init functions for different blocks. */
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extern qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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target_phys_addr_t base);
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void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
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qemu_irq *irq, target_phys_addr_t base);
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target_phys_addr_t base);
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void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
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qemu_irq *irq, target_phys_addr_t base);
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void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
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target_phys_addr_t base);
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target_phys_addr_t base);
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#define FLASH_SIZE 0x2000000
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#define INTMEM_SIZE (128 * 1024)
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static void *etraxfs_dmac;
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static uint32_t bootstrap_pc;
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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env->pregs[PR_CCS] &= ~I_FLAG;
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env->pc = bootstrap_pc;
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}
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static
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void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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@ -64,6 +68,7 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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int kernel_size;
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int i;
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ram_addr_t phys_ram;
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ram_addr_t phys_flash;
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ram_addr_t phys_intmem;
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/* init CPUs */
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@ -83,40 +88,42 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
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internal memory. Cached and uncached mappings. */
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phys_intmem = qemu_ram_alloc(INTMEM_SIZE);
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cpu_register_physical_memory(0xb8000000, INTMEM_SIZE,
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phys_intmem | IO_MEM_RAM);
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cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
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phys_intmem | IO_MEM_RAM);
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cpu_register_physical_memory(0xb8000000, INTMEM_SIZE,
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phys_intmem | IO_MEM_RAM);
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cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
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phys_intmem | IO_MEM_RAM);
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cpu_register_physical_memory(0, FLASH_SIZE, IO_MEM_ROM);
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cpu_register_physical_memory(0x80000000, FLASH_SIZE, IO_MEM_ROM);
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cpu_register_physical_memory(0x04000000, FLASH_SIZE, IO_MEM_ROM);
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cpu_register_physical_memory(0x84000000, FLASH_SIZE,
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0x04000000 | IO_MEM_ROM);
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phys_flash = qemu_ram_alloc(FLASH_SIZE);
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i = drive_get_index(IF_PFLASH, 0, 0);
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pflash_cfi02_register(0x80000000, qemu_ram_alloc(FLASH_SIZE),
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drives_table[i].bdrv, (64 * 1024),
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FLASH_SIZE >> 16,
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1, 2, 0x0000, 0x0000, 0x0000, 0x0000, 0x555, 0x2aa);
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pflash_cfi02_register(0x80000000, phys_flash,
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drives_table[i].bdrv, (64 * 1024),
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FLASH_SIZE >> 16,
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1, 2, 0x0000, 0x0000, 0x0000, 0x0000,
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0x555, 0x2aa);
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pflash_cfi02_register(0x0, phys_flash,
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drives_table[i].bdrv, (64 * 1024),
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FLASH_SIZE >> 16,
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1, 2, 0x0000, 0x0000, 0x0000, 0x0000,
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0x555, 0x2aa);
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pic = etraxfs_pic_init(env, 0xb001c000);
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etraxfs_dmac = etraxfs_dmac_init(env, 0xb0000000, 10);
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for (i = 0; i < 10; i++) {
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/* On ETRAX, odd numbered channels are inputs. */
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etraxfs_dmac_connect(etraxfs_dmac, i, pic + 7 + i, i & 1);
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/* On ETRAX, odd numbered channels are inputs. */
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etraxfs_dmac_connect(etraxfs_dmac, i, pic + 7 + i, i & 1);
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}
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/* Add the two ethernet blocks. */
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eth[0] = etraxfs_eth_init(&nd_table[0], env, pic + 25, 0xb0034000);
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if (nb_nics > 1)
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eth[1] = etraxfs_eth_init(&nd_table[1], env, pic + 26, 0xb0036000);
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eth[1] = etraxfs_eth_init(&nd_table[1], env, pic + 26, 0xb0036000);
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/* The DMA Connector block is missing, hardwire things for now. */
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etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
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etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
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if (eth[1]) {
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etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
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etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
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etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
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etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
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}
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/* 2 timers. */
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@ -124,40 +131,31 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
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etraxfs_timer_init(env, pic + 0x1b, 0xb005e000);
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for (i = 0; i < 4; i++) {
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if (serial_hds[i]) {
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etraxfs_ser_init(env, pic + 0x14 + i,
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serial_hds[i], 0xb0026000 + i * 0x2000);
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}
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if (serial_hds[i]) {
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etraxfs_ser_init(env, pic + 0x14 + i,
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serial_hds[i], 0xb0026000 + i * 0x2000);
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}
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}
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if (kernel_filename) {
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#if 1
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/* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis devboard
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SDK. */
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kernel_size = load_elf(kernel_filename, 0, &env->pc, NULL, NULL);
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/* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
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devboard SDK. */
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kernel_size = load_elf(kernel_filename, 0,
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&bootstrap_pc, NULL, NULL);
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#else
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/* Takes a kimage from the axis devboard SDK. */
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kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
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env->pc = 0x40004000;
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/* Takes a kimage from the axis devboard SDK. */
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kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
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bootstrap_pc = 0x40004000;
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/* magic for boot. */
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env->regs[8] = 0x56902387;
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env->regs[9] = 0x40004000 + kernel_size;
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#endif
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/* magic for boot. */
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env->regs[8] = 0x56902387;
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env->regs[9] = 0x40004000 + kernel_size;
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{
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unsigned char *ptr = phys_ram_base + 0x4000;
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int i;
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for (i = 0; i < 8; i++)
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{
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printf ("%2.2x ", ptr[i]);
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}
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printf("\n");
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}
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env->pc = bootstrap_pc;
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printf ("pc =%x\n", env->pc);
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printf ("ram size =%ld\n", ram_size);
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printf ("kernel name =%s\n", kernel_filename);
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printf ("kernel size =%d\n", kernel_size);
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printf ("cpu haltd =%d\n", env->halted);
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}
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void DMA_run(void)
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@ -169,5 +167,5 @@ QEMUMachine bareetraxfs_machine = {
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"bareetraxfs",
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"Bare ETRAX FS board",
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bareetraxfs_init,
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0x4000000,
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0x8000000,
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};
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@ -24,6 +24,7 @@
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#include <stdio.h>
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#include <sys/time.h>
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#include "hw.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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#define D(x)
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@ -36,6 +37,7 @@
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#define RW_TMR1_CTRL 0x18
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#define R_TIME 0x38
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#define RW_WD_CTRL 0x40
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#define R_WD_STAT 0x44
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#define RW_INTR_MASK 0x48
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#define RW_ACK_INTR 0x4c
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#define R_INTR 0x50
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@ -46,8 +48,12 @@ struct fs_timer_t {
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qemu_irq *irq;
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target_phys_addr_t base;
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QEMUBH *bh;
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ptimer_state *ptimer;
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QEMUBH *bh_t0;
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QEMUBH *bh_t1;
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QEMUBH *bh_wd;
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ptimer_state *ptimer_t0;
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ptimer_state *ptimer_t1;
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ptimer_state *ptimer_wd;
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struct timeval last;
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/* Control registers. */
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@ -59,6 +65,8 @@ struct fs_timer_t {
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uint32_t r_tmr1_data;
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uint32_t rw_tmr1_ctrl;
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uint32_t rw_wd_ctrl;
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uint32_t rw_intr_mask;
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uint32_t rw_ack_intr;
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uint32_t r_intr;
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@ -114,15 +122,28 @@ timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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}
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#define TIMER_SLOWDOWN 1
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static void update_ctrl(struct fs_timer_t *t)
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static void update_ctrl(struct fs_timer_t *t, int tnum)
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{
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unsigned int op;
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unsigned int freq;
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unsigned int freq_hz;
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unsigned int div;
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uint32_t ctrl;
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ptimer_state *timer;
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op = t->rw_tmr0_ctrl & 3;
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freq = t->rw_tmr0_ctrl >> 2;
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if (tnum == 0) {
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ctrl = t->rw_tmr0_ctrl;
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div = t->rw_tmr0_div;
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timer = t->ptimer_t0;
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} else {
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ctrl = t->rw_tmr1_ctrl;
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div = t->rw_tmr1_div;
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timer = t->ptimer_t1;
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}
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op = ctrl & 3;
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freq = ctrl >> 2;
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freq_hz = 32000000;
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switch (freq)
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@ -134,33 +155,32 @@ static void update_ctrl(struct fs_timer_t *t)
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case 4: freq_hz = 29493000; break;
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case 5: freq_hz = 32000000; break;
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case 6: freq_hz = 32768000; break;
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case 7: freq_hz = 100000000; break;
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case 7: freq_hz = 100001000; break;
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default:
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abort();
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break;
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}
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D(printf ("freq_hz=%d div=%d\n", freq_hz, t->rw_tmr0_div));
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div = t->rw_tmr0_div * TIMER_SLOWDOWN;
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D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
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div = div * TIMER_SLOWDOWN;
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div >>= 15;
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freq_hz >>= 15;
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ptimer_set_freq(t->ptimer, freq_hz);
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ptimer_set_limit(t->ptimer, div, 0);
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ptimer_set_freq(timer, freq_hz);
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ptimer_set_limit(timer, div, 0);
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switch (op)
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{
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case 0:
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/* Load. */
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ptimer_set_limit(t->ptimer, div, 1);
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ptimer_run(t->ptimer, 1);
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ptimer_set_limit(timer, div, 1);
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break;
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case 1:
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/* Hold. */
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ptimer_stop(t->ptimer);
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ptimer_stop(timer);
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break;
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case 2:
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/* Run. */
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ptimer_run(t->ptimer, 0);
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ptimer_run(timer, 0);
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break;
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default:
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abort();
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@ -180,13 +200,55 @@ static void timer_update_irq(struct fs_timer_t *t)
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qemu_irq_lower(t->irq[0]);
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}
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static void timer_hit(void *opaque)
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static void timer0_hit(void *opaque)
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{
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struct fs_timer_t *t = opaque;
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t->r_intr |= 1;
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timer_update_irq(t);
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}
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static void timer1_hit(void *opaque)
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{
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struct fs_timer_t *t = opaque;
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t->r_intr |= 2;
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timer_update_irq(t);
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}
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static void watchdog_hit(void *opaque)
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{
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qemu_system_reset_request();
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}
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static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
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{
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unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
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unsigned int wd_key = t->rw_wd_ctrl >> 9;
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unsigned int wd_cnt = t->rw_wd_ctrl & 511;
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unsigned int new_key = value >> 9 & ((1 << 7) - 1);
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unsigned int new_cmd = (value >> 8) & 1;
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/* If the watchdog is enabled, they written key must match the
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complement of the previous. */
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wd_key = ~wd_key & ((1 << 7) - 1);
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if (wd_en && wd_key != new_key)
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return;
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D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
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wd_en, new_key, wd_key, wd_cmd, wd_cnt));
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ptimer_set_freq(t->ptimer_wd, 760);
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if (wd_cnt == 0)
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wd_cnt = 256;
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ptimer_set_count(t->ptimer_wd, wd_cnt);
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if (new_cmd)
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ptimer_run(t->ptimer_wd, 1);
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else
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ptimer_stop(t->ptimer_wd);
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t->rw_wd_ctrl = value;
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}
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static void
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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@ -203,13 +265,15 @@ timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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case RW_TMR0_CTRL:
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D(printf ("RW_TMR0_CTRL=%x\n", value));
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t->rw_tmr0_ctrl = value;
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update_ctrl(t);
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update_ctrl(t, 0);
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break;
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case RW_TMR1_DIV:
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t->rw_tmr1_div = value;
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break;
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case RW_TMR1_CTRL:
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D(printf ("RW_TMR1_CTRL=%x\n", value));
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t->rw_tmr1_ctrl = value;
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update_ctrl(t, 1);
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break;
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case RW_INTR_MASK:
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D(printf ("RW_INTR_MASK=%x\n", value));
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@ -217,7 +281,7 @@ timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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timer_update_irq(t);
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break;
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case RW_WD_CTRL:
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D(printf ("RW_WD_CTRL=%x\n", value));
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timer_watchdog_update(t, value);
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break;
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case RW_ACK_INTR:
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t->rw_ack_intr = value;
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@ -232,17 +296,30 @@ timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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}
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static CPUReadMemoryFunc *timer_read[] = {
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&timer_rinvalid,
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&timer_rinvalid,
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&timer_readl,
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&timer_rinvalid,
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&timer_rinvalid,
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&timer_readl,
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};
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static CPUWriteMemoryFunc *timer_write[] = {
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&timer_winvalid,
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&timer_winvalid,
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&timer_writel,
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&timer_winvalid,
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&timer_winvalid,
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&timer_writel,
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};
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static void etraxfs_timer_reset(void *opaque)
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{
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struct fs_timer_t *t = opaque;
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ptimer_stop(t->ptimer_t0);
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ptimer_stop(t->ptimer_t1);
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ptimer_stop(t->ptimer_wd);
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t->rw_wd_ctrl = 0;
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t->r_intr = 0;
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t->rw_intr_mask = 0;
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qemu_irq_lower(t->irq[0]);
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}
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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target_phys_addr_t base)
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{
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@ -253,12 +330,18 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
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if (!t)
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return;
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t->bh = qemu_bh_new(timer_hit, t);
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t->ptimer = ptimer_init(t->bh);
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t->bh_t0 = qemu_bh_new(timer0_hit, t);
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t->bh_t1 = qemu_bh_new(timer1_hit, t);
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t->bh_wd = qemu_bh_new(watchdog_hit, t);
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t->ptimer_t0 = ptimer_init(t->bh_t0);
|
||||
t->ptimer_t1 = ptimer_init(t->bh_t1);
|
||||
t->ptimer_wd = ptimer_init(t->bh_wd);
|
||||
t->irq = irqs;
|
||||
t->env = env;
|
||||
t->base = base;
|
||||
|
||||
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
|
||||
cpu_register_physical_memory (base, 0x5c, timer_regs);
|
||||
|
||||
qemu_register_reset(etraxfs_timer_reset, t);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue