mirror of https://gitee.com/openkylin/qemu.git
added CMD646 PCI IDE controller support - better IRQ handling - added IDE flush cache command - added work around for Darwin/PPC to select IDE drive
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1449 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
0aa6a4a250
commit
5457c8ceeb
237
hw/ide.c
237
hw/ide.c
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@ -296,8 +296,9 @@ typedef struct IDEState {
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int cylinders, heads, sectors;
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int64_t nb_sectors;
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int mult_sectors;
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SetIRQFunc *set_irq;
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void *irq_opaque;
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int irq;
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openpic_t *openpic;
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PCIDevice *pci_dev;
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struct BMDMAState *bmdma;
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int drive_serial;
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@ -342,6 +343,18 @@ typedef struct IDEState {
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#define BM_CMD_START 0x01
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#define BM_CMD_READ 0x08
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#define IDE_TYPE_PIIX3 0
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#define IDE_TYPE_CMD646 1
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/* CMD646 specific */
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#define MRDMODE 0x71
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#define MRDMODE_INTR_CH0 0x04
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#define MRDMODE_INTR_CH1 0x08
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#define MRDMODE_BLK_CH0 0x10
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#define MRDMODE_BLK_CH1 0x20
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#define UDIDETCR0 0x73
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#define UDIDETCR1 0x7B
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typedef int IDEDMAFunc(IDEState *s,
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target_phys_addr_t phys_addr,
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int transfer_size1);
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@ -350,6 +363,8 @@ typedef struct BMDMAState {
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uint8_t cmd;
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uint8_t status;
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uint32_t addr;
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struct PCIIDEState *pci_dev;
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/* current transfer state */
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IDEState *ide_if;
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IDEDMAFunc *dma_cb;
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@ -359,6 +374,7 @@ typedef struct PCIIDEState {
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PCIDevice dev;
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IDEState ide_if[4];
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BMDMAState bmdma[2];
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int type; /* see IDE_TYPE_xxx */
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} PCIIDEState;
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static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb);
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@ -502,17 +518,10 @@ static inline void ide_set_irq(IDEState *s)
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{
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BMDMAState *bm = s->bmdma;
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if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
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if (bm)
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if (bm) {
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bm->status |= BM_STATUS_INT;
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#ifdef TARGET_PPC
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if (s->openpic)
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openpic_set_irq(s->openpic, s->irq, 1);
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else
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#endif
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if (s->irq == 16)
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pci_set_irq(s->pci_dev, 0, 1);
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else
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pic_set_irq(s->irq, 1);
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}
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s->set_irq(s->irq_opaque, s->irq, 1);
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}
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}
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@ -814,7 +823,8 @@ static void cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
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case 2352:
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/* sync bytes */
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buf[0] = 0x00;
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memset(buf + 1, 0xff, 11);
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memset(buf + 1, 0xff, 10);
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buf[11] = 0x00;
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buf += 12;
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/* MSF */
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lba_to_msf(buf, lba);
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@ -942,6 +952,9 @@ static int ide_atapi_cmd_read_dma_cb(IDEState *s,
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transfer_size = transfer_size1;
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while (transfer_size > 0) {
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#ifdef DEBUG_IDE_ATAPI
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printf("transfer_size: %d phys_addr=%08x\n", transfer_size, phys_addr);
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#endif
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if (s->packet_transfer_size <= 0)
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break;
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len = s->cd_sector_size - s->io_buffer_index;
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@ -1019,9 +1032,8 @@ static int cdrom_read_toc(IDEState *s, uint8_t *buf, int msf, int start_track)
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*q++ = 0; /* reserved */
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if (msf) {
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*q++ = 0; /* reserved */
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*q++ = 0; /* minute */
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*q++ = 2; /* second */
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*q++ = 0; /* frame */
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lba_to_msf(q, 0);
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q += 3;
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} else {
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/* sector 0 */
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cpu_to_ube32(q, 0);
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@ -1476,6 +1488,11 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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unit = (val >> 4) & 1;
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s = ide_if + unit;
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ide_if->cur_drive = s;
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#ifdef TARGET_PPC
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/* XXX: currently a workaround for Darwin/PPC. Need to check
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the IDE spec to see if it is correct */
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ide_set_signature(s);
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#endif
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break;
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default:
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case 7:
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@ -1596,6 +1613,7 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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break;
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case WIN_STANDBYNOW1:
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case WIN_IDLEIMMEDIATE:
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case WIN_FLUSH_CACHE:
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s->status = READY_STAT;
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ide_set_irq(s);
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break;
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@ -1697,15 +1715,7 @@ static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
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ret = 0;
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else
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ret = s->status;
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#ifdef TARGET_PPC
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if (s->openpic)
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openpic_set_irq(s->openpic, s->irq, 0);
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else
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#endif
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if (s->irq == 16)
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pci_set_irq(s->pci_dev, 0, 0);
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else
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pic_set_irq(s->irq, 0);
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s->set_irq(s->irq_opaque, s->irq, 0);
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break;
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}
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#ifdef DEBUG_IDE
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@ -1898,8 +1908,9 @@ static int guess_disk_lchs(IDEState *s,
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return -1;
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}
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static void ide_init2(IDEState *ide_state, int irq,
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BlockDriverState *hd0, BlockDriverState *hd1)
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static void ide_init2(IDEState *ide_state,
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BlockDriverState *hd0, BlockDriverState *hd1,
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SetIRQFunc *set_irq, void *irq_opaque, int irq)
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{
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IDEState *s;
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static int drive_serial = 1;
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@ -1960,6 +1971,8 @@ static void ide_init2(IDEState *ide_state, int irq,
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}
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}
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s->drive_serial = drive_serial++;
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s->set_irq = set_irq;
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s->irq_opaque = irq_opaque;
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s->irq = irq;
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s->sector_write_timer = qemu_new_timer(vm_clock,
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ide_sector_write_timer_cb, s);
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@ -1995,13 +2008,15 @@ void isa_ide_init(int iobase, int iobase2, int irq,
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if (!ide_state)
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return;
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ide_init2(ide_state, irq, hd0, hd1);
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ide_init2(ide_state, hd0, hd1, pic_set_irq_new, NULL, irq);
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ide_init_ioport(ide_state, iobase, iobase2);
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}
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/***********************************************************/
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/* PCI IDE definitions */
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static void cmd646_update_irq(PCIIDEState *d);
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static void ide_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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@ -2082,17 +2097,6 @@ static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb)
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}
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}
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static uint32_t bmdma_cmd_readb(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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val = bm->cmd;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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return val;
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}
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static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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@ -2112,24 +2116,77 @@ static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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}
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}
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static uint32_t bmdma_status_readb(void *opaque, uint32_t addr)
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static uint32_t bmdma_readb(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev;
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uint32_t val;
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val = bm->status;
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 1:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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val = pci_dev->dev.config[MRDMODE];
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} else {
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val = 0xff;
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}
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break;
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case 2:
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val = bm->status;
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break;
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case 3:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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if (bm == &pci_dev->bmdma[0])
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val = pci_dev->dev.config[UDIDETCR0];
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else
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val = pci_dev->dev.config[UDIDETCR1];
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} else {
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val = 0xff;
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}
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_status_writeb(void *opaque, uint32_t addr, uint32_t val)
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static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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switch(addr & 3) {
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case 1:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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pci_dev->dev.config[MRDMODE] =
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(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
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cmd646_update_irq(pci_dev);
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}
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break;
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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case 3:
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pci_dev = bm->pci_dev;
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if (pci_dev->type == IDE_TYPE_CMD646) {
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if (bm == &pci_dev->bmdma[0])
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pci_dev->dev.config[UDIDETCR0] = val;
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else
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pci_dev->dev.config[UDIDETCR1] = val;
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}
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break;
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}
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}
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static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
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@ -2162,12 +2219,12 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num,
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BMDMAState *bm = &d->bmdma[i];
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d->ide_if[2 * i].bmdma = bm;
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d->ide_if[2 * i + 1].bmdma = bm;
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register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
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register_ioport_read(addr, 1, 1, bmdma_cmd_readb, bm);
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bm->pci_dev = (PCIIDEState *)pci_dev;
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register_ioport_write(addr + 2, 1, 1, bmdma_status_writeb, bm);
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register_ioport_read(addr + 2, 1, 1, bmdma_status_readb, bm);
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register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
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register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
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register_ioport_read(addr, 4, 1, bmdma_readb, bm);
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register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
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register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
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@ -2175,29 +2232,62 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num,
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}
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}
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/* hd_table must contain 4 block drivers */
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void pci_ide_init(PCIBus *bus, BlockDriverState **hd_table)
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/* XXX: call it also when the MRDMODE is changed from the PCI config
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registers */
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static void cmd646_update_irq(PCIIDEState *d)
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{
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int pci_level;
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pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
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((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
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pci_set_irq((PCIDevice *)d, 0, pci_level);
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}
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/* the PCI irq level is the logical OR of the two channels */
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static void cmd646_set_irq(void *opaque, int channel, int level)
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{
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PCIIDEState *d = opaque;
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int irq_mask;
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irq_mask = MRDMODE_INTR_CH0 << channel;
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if (level)
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d->dev.config[MRDMODE] |= irq_mask;
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else
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d->dev.config[MRDMODE] &= ~irq_mask;
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cmd646_update_irq(d);
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}
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/* CMD646 PCI IDE controller */
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void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
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int secondary_ide_enabled)
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{
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PCIIDEState *d;
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uint8_t *pci_conf;
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int i;
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d = (PCIIDEState *)pci_register_device(bus, "IDE", sizeof(PCIIDEState),
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d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
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sizeof(PCIIDEState),
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-1,
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NULL, NULL);
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d->type = IDE_TYPE_CMD646;
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pci_conf = d->dev.config;
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pci_conf[0x00] = 0x86; // Intel
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pci_conf[0x01] = 0x80;
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pci_conf[0x02] = 0x00; // fake
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pci_conf[0x03] = 0x01; // fake
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pci_conf[0x00] = 0x95; // CMD646
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pci_conf[0x01] = 0x10;
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pci_conf[0x02] = 0x46;
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pci_conf[0x03] = 0x06;
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pci_conf[0x08] = 0x07; // IDE controller revision
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pci_conf[0x09] = 0x8f;
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pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
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pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
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pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
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pci_conf[0x2c] = 0x86; // subsys vendor
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pci_conf[0x2d] = 0x80; // subsys vendor
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pci_conf[0x2e] = 0x00; // fake
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pci_conf[0x2f] = 0x01; // fake
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pci_conf[0x0e] = 0x00; // header_type
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if (secondary_ide_enabled) {
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/* XXX: if not enabled, really disable the seconday IDE controller */
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pci_conf[0x51] = 0x80; /* enable IDE1 */
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}
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pci_register_io_region((PCIDevice *)d, 0, 0x8,
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PCI_ADDRESS_SPACE_IO, ide_map);
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@ -2211,11 +2301,13 @@ void pci_ide_init(PCIBus *bus, BlockDriverState **hd_table)
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PCI_ADDRESS_SPACE_IO, bmdma_map);
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pci_conf[0x3d] = 0x01; // interrupt on pin 1
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for(i = 0; i < 4; i++)
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d->ide_if[i].pci_dev = (PCIDevice *)d;
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ide_init2(&d->ide_if[0], 16, hd_table[0], hd_table[1]);
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ide_init2(&d->ide_if[2], 16, hd_table[2], hd_table[3]);
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ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
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cmd646_set_irq, d, 0);
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ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
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cmd646_set_irq, d, 1);
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}
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/* hd_table must contain 4 block drivers */
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@ -2230,6 +2322,8 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table)
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sizeof(PCIIDEState),
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((PCIDevice *)piix3_state)->devfn + 1,
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NULL, NULL);
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d->type = IDE_TYPE_PIIX3;
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pci_conf = d->dev.config;
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pci_conf[0x00] = 0x86; // Intel
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pci_conf[0x01] = 0x80;
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@ -2242,8 +2336,10 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table)
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pci_register_io_region((PCIDevice *)d, 4, 0x10,
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PCI_ADDRESS_SPACE_IO, bmdma_map);
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ide_init2(&d->ide_if[0], 14, hd_table[0], hd_table[1]);
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ide_init2(&d->ide_if[2], 15, hd_table[2], hd_table[3]);
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ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
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pic_set_irq_new, NULL, 14);
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ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
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pic_set_irq_new, NULL, 15);
|
||||
ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
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||||
ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
|
||||
}
|
||||
|
|
@ -2361,15 +2457,14 @@ static CPUReadMemoryFunc *pmac_ide_read[] = {
|
|||
/* PowerMac uses memory mapped registers, not I/O. Return the memory
|
||||
I/O index to access the ide. */
|
||||
int pmac_ide_init (BlockDriverState **hd_table,
|
||||
openpic_t *openpic, int irq)
|
||||
SetIRQFunc *set_irq, void *irq_opaque, int irq)
|
||||
{
|
||||
IDEState *ide_if;
|
||||
int pmac_ide_memory;
|
||||
|
||||
ide_if = qemu_mallocz(sizeof(IDEState) * 2);
|
||||
ide_init2(&ide_if[0], irq, hd_table[0], hd_table[1]);
|
||||
ide_if[0].openpic = openpic;
|
||||
ide_if[1].openpic = openpic;
|
||||
ide_init2(&ide_if[0], hd_table[0], hd_table[1],
|
||||
set_irq, irq_opaque, irq);
|
||||
|
||||
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
|
||||
pmac_ide_write, &ide_if[0]);
|
||||
|
|
|
|||
Loading…
Reference in New Issue