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target-microblaze: Introduce a use-msr-instr property 

Introduce a use-msr-instr property making msr instructions
optional.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias 2017-06-20 13:13:26 +02:00
parent 9b9643181a
commit 5683750909
3 changed files with 5 additions and 3 deletions
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5
target/microblaze/cpu.c
View File

@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| PVR2_D_LMB_MASK \ | PVR2_D_LMB_MASK \
| PVR2_I_OPB_MASK \ | PVR2_I_OPB_MASK \
| PVR2_I_LMB_MASK \ | PVR2_I_LMB_MASK \
| PVR2_USE_MSR_INSTR \
| PVR2_USE_PCMP_INSTR \ | PVR2_USE_PCMP_INSTR \
| PVR2_FPU_EXC_MASK \ | PVR2_FPU_EXC_MASK \
| 0; | 0;
@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
(cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
(cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
(cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
(cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0);
env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
PVR5_DCACHE_WRITEBACK_MASK : 0; PVR5_DCACHE_WRITEBACK_MASK : 0;
@ -241,6 +241,7 @@ static Property mb_properties[] = {
DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
false), false),

1
target/microblaze/cpu.h
View File

@ -301,6 +301,7 @@ struct MicroBlazeCPU {
uint8_t use_hw_mul; uint8_t use_hw_mul;
bool use_barrel; bool use_barrel;
bool use_div; bool use_div;
bool use_msr_instr;
bool use_mmu; bool use_mmu;
bool dcache_writeback; bool dcache_writeback;
bool endi; bool endi;

2
target/microblaze/translate.c
View File

@ -443,7 +443,7 @@ static void dec_msr(DisasContext *dc)
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
dc->rd, dc->imm); dc->rd, dc->imm);
if (!(dc->cpu->env.pvr.regs[2] & PVR2_USE_MSR_INSTR)) { if (!dc->cpu->cfg.use_msr_instr) {
/* nop??? */ /* nop??? */
return; return;
} }