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target-arm: Fix RVBAR_EL1 register encoding 

Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1

Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1422029835-4696-2-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Greg Bellows 2015-02-05 13:37:21 +00:00 committed by Peter Maydell
parent 8b47b7da29
commit 569b49f864
1 changed files with 1 additions and 1 deletions
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2
target-arm/helper.c
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@ -3055,7 +3055,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
};
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);