From 57d69a91c41e71ae5f5181c6dedd62dc866234b5 Mon Sep 17 00:00:00 2001
From: balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Tue, 6 May 2008 14:45:30 +0000
Subject: [PATCH] Force correct evaluation order in a a == b != c condition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4358 c046a42c-6fe2-441c-8c8c-71466251a162
---
 hw/arm_gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 82577301b0..7f67c5276d 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -62,7 +62,7 @@ typedef struct gic_irq_state
 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
-#define GIC_TEST_LEVEL(irq, cm) (s->irq_state[irq].level & (cm)) != 0
+#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger