mirror of https://gitee.com/openkylin/qemu.git
target/arm: Add v8M stack limit checks on NS function calls
Check the v8M stack limits when pushing the frame for a non-secure function call via BLXNS. In order to be able to generate the exception we need to promote raise_exception() from being local to op_helper.c so we can call it from helper.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181002163556.10279-8-peter.maydell@linaro.org
This commit is contained in:
parent
c32da7aa62
commit
597610eb39
|
@ -6738,6 +6738,10 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
|
||||||
"BLXNS with misaligned SP is UNPREDICTABLE\n");
|
"BLXNS with misaligned SP is UNPREDICTABLE\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (sp < v7m_sp_limit(env)) {
|
||||||
|
raise_exception(env, EXCP_STKOF, 0, 1);
|
||||||
|
}
|
||||||
|
|
||||||
saved_psr = env->v7m.exception;
|
saved_psr = env->v7m.exception;
|
||||||
if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {
|
if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) {
|
||||||
saved_psr |= XPSR_SFPA;
|
saved_psr |= XPSR_SFPA;
|
||||||
|
|
|
@ -94,6 +94,15 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
|
||||||
#define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
|
#define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
|
||||||
#define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
|
#define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* raise_exception: Raise the specified exception.
|
||||||
|
* Raise a guest exception with the specified value, syndrome register
|
||||||
|
* and target exception level. This should be called from helper functions,
|
||||||
|
* and never returns because we will longjump back up to the CPU main loop.
|
||||||
|
*/
|
||||||
|
void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp,
|
||||||
|
uint32_t syndrome, uint32_t target_el);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* For AArch64, map a given EL to an index in the banked_spsr array.
|
* For AArch64, map a given EL to an index in the banked_spsr array.
|
||||||
* Note that this mapping and the AArch32 mapping defined in bank_number()
|
* Note that this mapping and the AArch32 mapping defined in bank_number()
|
||||||
|
|
|
@ -28,8 +28,8 @@
|
||||||
#define SIGNBIT (uint32_t)0x80000000
|
#define SIGNBIT (uint32_t)0x80000000
|
||||||
#define SIGNBIT64 ((uint64_t)1 << 63)
|
#define SIGNBIT64 ((uint64_t)1 << 63)
|
||||||
|
|
||||||
static void raise_exception(CPUARMState *env, uint32_t excp,
|
void raise_exception(CPUARMState *env, uint32_t excp,
|
||||||
uint32_t syndrome, uint32_t target_el)
|
uint32_t syndrome, uint32_t target_el)
|
||||||
{
|
{
|
||||||
CPUState *cs = CPU(arm_env_get_cpu(env));
|
CPUState *cs = CPU(arm_env_get_cpu(env));
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue