mirror of https://gitee.com/openkylin/qemu.git
msix: Allow full specification of MSIX layout
Finally, complete the fully specified interface. msix_add_config() gets folded into msix_init() because we now have quite a few parameters to pass and rolling it in let's us error earlier, avoiding the ugly unwind exit path. msix_mmio_setup() also gets rolled in, just because it's redundant to rediscover offsets when we already have them for such a tiny function. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Alex Williamson
Michael S. Tsirkin
parent
d35e428c84
commit
5a2c202981
145
hw/msix.c
145
hw/msix.c
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@ -27,14 +27,6 @@
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#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
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#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
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/* How much space does an MSIX table need. */
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/* The spec requires giving the table structure
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* a 4K aligned region all by itself. */
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#define MSIX_PAGE_SIZE 0x1000
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/* Reserve second half of the page for pending bits */
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#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
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#define MSIX_MAX_ENTRIES 32
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static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
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{
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uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
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@ -45,47 +37,6 @@ static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
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return msg;
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}
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/* Add MSI-X capability to the config space for the device. */
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/* Given a bar and its size, add MSI-X table on top of it
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* and fill MSI-X capability in the config space.
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* Original bar size must be a power of 2 or 0.
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* New bar size is returned. */
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static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size)
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{
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int config_offset;
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uint8_t *config;
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if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
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return -EINVAL;
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if (bar_size > 0x80000000)
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return -ENOSPC;
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/* Require aligned offset for MSI-X structures */
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if (bar_size & ~(MSIX_PAGE_SIZE - 1)) {
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return -EINVAL;
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}
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config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
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0, MSIX_CAP_LENGTH);
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if (config_offset < 0)
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return config_offset;
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config = pdev->config + config_offset;
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pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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/* Table on top of BAR */
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pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
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/* Pending bits on top of that */
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pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
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bar_nr);
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pdev->msix_cap = config_offset;
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/* Make flags bit writable. */
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pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
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MSIX_MASKALL_MASK;
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pdev->msix_function_masked = true;
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return 0;
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}
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static uint8_t msix_pending_mask(int vector)
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{
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return 1 << (vector % 8);
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@ -242,20 +193,6 @@ static const MemoryRegionOps msix_pba_mmio_ops = {
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},
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};
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static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
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{
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uint8_t *config = d->config + d->msix_cap;
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uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
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uint32_t table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
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uint32_t pba = pci_get_long(config + PCI_MSIX_PBA);
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uint32_t pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
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/* TODO: for assigned devices, we'll want to make it possible to map
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* pending bits separately in case they are in a separate bar. */
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memory_region_add_subregion(bar, table_offset, &d->msix_table_mmio);
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memory_region_add_subregion(bar, pba_offset, &d->msix_pba_mmio);
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}
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static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
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{
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int vector;
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@ -270,57 +207,71 @@ static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
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}
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}
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/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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* modified, it should be retrieved with msix_bar_size. */
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/* Initialize the MSI-X structures */
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int msix_init(struct PCIDevice *dev, unsigned short nentries,
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MemoryRegion *bar,
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unsigned bar_nr, unsigned bar_size)
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MemoryRegion *table_bar, uint8_t table_bar_nr,
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unsigned table_offset, MemoryRegion *pba_bar,
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uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos)
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{
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int ret;
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int cap;
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unsigned table_size, pba_size;
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uint8_t *config;
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/* Nothing to do if MSI is not supported by interrupt controller */
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if (!msi_supported) {
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return -ENOTSUP;
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}
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if (nentries > MSIX_MAX_ENTRIES)
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if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {
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return -EINVAL;
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}
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table_size = nentries * PCI_MSIX_ENTRY_SIZE;
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pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
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dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
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sizeof *dev->msix_entry_used);
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/* Sanity test: table & pba don't overlap, fit within BARs, min aligned */
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if ((table_bar_nr == pba_bar_nr &&
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ranges_overlap(table_offset, table_size, pba_offset, pba_size)) ||
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table_offset + table_size > memory_region_size(table_bar) ||
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pba_offset + pba_size > memory_region_size(pba_bar) ||
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(table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {
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return -EINVAL;
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}
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cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH);
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if (cap < 0) {
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return cap;
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}
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dev->msix_cap = cap;
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dev->cap_present |= QEMU_PCI_CAP_MSIX;
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config = dev->config + cap;
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pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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dev->msix_entries_nr = nentries;
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dev->msix_function_masked = true;
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pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr);
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pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr);
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/* Make flags bit writable. */
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dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
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MSIX_MASKALL_MASK;
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dev->msix_table = g_malloc0(table_size);
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dev->msix_pba = g_malloc0(pba_size);
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dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
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msix_mask_all(dev, nentries);
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memory_region_init_io(&dev->msix_table_mmio, &msix_table_mmio_ops, dev,
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"msix-table", table_size);
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memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
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memory_region_init_io(&dev->msix_pba_mmio, &msix_pba_mmio_ops, dev,
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"msix-pba", pba_size);
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memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
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dev->msix_entries_nr = nentries;
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ret = msix_add_config(dev, nentries, bar_nr, bar_size);
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if (ret)
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goto err_config;
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dev->cap_present |= QEMU_PCI_CAP_MSIX;
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msix_mmio_setup(dev, bar);
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return 0;
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err_config:
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dev->msix_entries_nr = 0;
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memory_region_destroy(&dev->msix_pba_mmio);
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g_free(dev->msix_pba);
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dev->msix_pba = NULL;
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memory_region_destroy(&dev->msix_table_mmio);
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g_free(dev->msix_table);
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dev->msix_table = NULL;
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g_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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return ret;
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}
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int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
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@ -335,7 +286,9 @@ int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
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* the upper half. Do not use these elsewhere!
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*/
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#define MSIX_EXCLUSIVE_BAR_SIZE 4096
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#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0
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#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)
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#define MSIX_EXCLUSIVE_CAP_OFFSET 0
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if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {
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return -EINVAL;
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@ -350,7 +303,9 @@ int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
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free(name);
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ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
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MSIX_EXCLUSIVE_BAR_SIZE);
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MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar,
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bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,
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MSIX_EXCLUSIVE_CAP_OFFSET);
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if (ret) {
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memory_region_destroy(&dev->msix_exclusive_bar);
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return ret;
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@ -373,7 +328,7 @@ static void msix_free_irq_entries(PCIDevice *dev)
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}
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/* Clean up resources for the device. */
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int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
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int msix_uninit(PCIDevice *dev, MemoryRegion *table_bar, MemoryRegion *pba_bar)
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{
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if (!msix_present(dev)) {
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return 0;
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@ -382,11 +337,11 @@ int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
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dev->msix_cap = 0;
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msix_free_irq_entries(dev);
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dev->msix_entries_nr = 0;
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memory_region_del_subregion(bar, &dev->msix_pba_mmio);
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memory_region_del_subregion(pba_bar, &dev->msix_pba_mmio);
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memory_region_destroy(&dev->msix_pba_mmio);
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g_free(dev->msix_pba);
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dev->msix_pba = NULL;
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memory_region_del_subregion(bar, &dev->msix_table_mmio);
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memory_region_del_subregion(table_bar, &dev->msix_table_mmio);
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memory_region_destroy(&dev->msix_table_mmio);
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g_free(dev->msix_table);
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dev->msix_table = NULL;
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@ -399,7 +354,7 @@ int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
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void msix_uninit_exclusive_bar(PCIDevice *dev)
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{
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if (msix_present(dev)) {
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msix_uninit(dev, &dev->msix_exclusive_bar);
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msix_uninit(dev, &dev->msix_exclusive_bar, &dev->msix_exclusive_bar);
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memory_region_destroy(&dev->msix_exclusive_bar);
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}
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}
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10
hw/msix.h
10
hw/msix.h
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@ -4,15 +4,17 @@
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#include "qemu-common.h"
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#include "pci.h"
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int msix_init(PCIDevice *pdev, unsigned short nentries,
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MemoryRegion *bar,
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unsigned bar_nr, unsigned bar_size);
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int msix_init(PCIDevice *dev, unsigned short nentries,
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MemoryRegion *table_bar, uint8_t table_bar_nr,
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unsigned table_offset, MemoryRegion *pba_bar,
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uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos);
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int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
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uint8_t bar_nr);
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void msix_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len);
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int msix_uninit(PCIDevice *d, MemoryRegion *bar);
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int msix_uninit(PCIDevice *dev, MemoryRegion *table_bar,
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MemoryRegion *pba_bar);
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void msix_uninit_exclusive_bar(PCIDevice *dev);
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unsigned int msix_nr_vectors_allocated(const PCIDevice *dev);
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