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target-arm queue: 

* Initial part of SVE implementation (currently disabled)
  * smmuv3: fix some minor Coverity issues
  * add model of Xilinx ZynqMP generic DMA controller
  * expose (most) Arm coprocessor/system registers to
    gdb via QEMU's gdbstub, for reads only
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180518' into staging

target-arm queue:
 * Initial part of SVE implementation (currently disabled)
 * smmuv3: fix some minor Coverity issues
 * add model of Xilinx ZynqMP generic DMA controller
 * expose (most) Arm coprocessor/system registers to
   gdb via QEMU's gdbstub, for reads only

# gpg: Signature made Fri 18 May 2018 18:18:27 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180518: (32 commits)
  target/arm: Implement SVE Permute - Extract Group
  target/arm: Implement SVE Integer Wide Immediate - Predicated Group
  target/arm: Implement SVE Bitwise Immediate Group
  target/arm: Implement SVE Element Count Group
  target/arm: Implement SVE floating-point trig select coefficient
  target/arm: Implement SVE floating-point exponential accelerator
  target/arm: Implement SVE Compute Vector Address Group
  target/arm: Implement SVE Bitwise Shift - Unpredicated Group
  target/arm: Implement SVE Stack Allocation Group
  target/arm: Implement SVE Index Generation Group
  target/arm: Implement SVE Integer Arithmetic - Unpredicated Group
  target/arm: Implement SVE Integer Multiply-Add Group
  target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group
  target/arm: Implement SVE bitwise shift by wide elements (predicated)
  target/arm: Implement SVE bitwise shift by vector (predicated)
  target/arm: Implement SVE bitwise shift by immediate (predicated)
  target/arm: Implement SVE Integer Reduction Group
  target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
  target/arm: Implement SVE Predicate Misc Group
  target/arm: Implement SVE Predicate Logical Operations Group
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-05-18 18:25:29 +01:00
parent d32e41a118 b94f8f60bd
commit 5bcf917ee3
22 changed files with 5778 additions and 116 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -206,3 +206,4 @@ trace-dtrace-root.h
trace-dtrace-root.dtrace
trace-ust-all.h
trace-ust-all.c
/target/arm/decode-sve.inc.c

10
gdbstub.c
View File

@ -675,6 +675,16 @@ static const char *get_feature_xml(const char *p, const char **newp,
}
return target_xml;
}
if (cc->gdb_get_dynamic_xml) {
CPUState *cpu = first_cpu;
char *xmlname = g_strndup(p, len);
const char *xml = cc->gdb_get_dynamic_xml(cpu, xmlname);
g_free(xmlname);
if (xml) {
return xml;
}
}
for (i = 0; ; i++) {
name = xml_builtin[i][0];
if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))

4
hw/arm/smmu-common.c
View File

@ -83,9 +83,9 @@ static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz)
static inline hwaddr get_block_pte_address(uint64_t pte, int level,
int granule_sz, uint64_t *bsz)
{
int n = (granule_sz - 3) * (4 - level) + 3;
int n = level_shift(level, granule_sz);
*bsz = 1 << n;
*bsz = 1ULL << n;
return PTE_ADDRESS(pte, n);
}

2
hw/arm/smmuv3.c
View File

@ -143,7 +143,7 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt)
void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)
{
Evt evt;
Evt evt = {};
MemTxResult r;
if (!smmuv3_eventq_enabled(s)) {

53
hw/arm/xlnx-zynqmp.c
View File

@ -90,6 +90,24 @@ static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
19, 20,
};
static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
};
static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
124, 125, 126, 127, 128, 129, 130, 131
};
static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
};
static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
77, 78, 79, 80, 81, 82, 83, 84
};
typedef struct XlnxZynqMPGICRegion {
int region_index;
uint32_t address;
@ -197,6 +215,16 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC);
qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default());
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
object_initialize(&s->gdma[i], sizeof(s->gdma[i]), TYPE_XLNX_ZDMA);
qdev_set_parent_bus(DEVICE(&s->gdma[i]), sysbus_get_default());
}
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
object_initialize(&s->adma[i], sizeof(s->adma[i]), TYPE_XLNX_ZDMA);
qdev_set_parent_bus(DEVICE(&s->adma[i]), sysbus_get_default());
}
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@ -492,6 +520,31 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
gic_spi[gdma_ch_intr[i]]);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
gic_spi[adma_ch_intr[i]]);
}
}
static Property xlnx_zynqmp_props[] = {

1
hw/dma/Makefile.objs
View File

@ -10,6 +10,7 @@ common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
obj-$(CONFIG_XLNX_ZYNQMP) += xlnx_dpdma.o
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx_dpdma.o
common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zdma.o
obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o

832
hw/dma/xlnx-zdma.c Normal file
View File

@ -0,0 +1,832 @@
/*
* QEMU model of the ZynqMP generic DMA
*
* Copyright (c) 2014 Xilinx Inc.
* Copyright (c) 2018 FEIMTECH AB
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>,
* Francisco Iglesias <francisco.iglesias@feimtech.se>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "hw/dma/xlnx-zdma.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "qapi/error.h"
#ifndef XLNX_ZDMA_ERR_DEBUG
#define XLNX_ZDMA_ERR_DEBUG 0
#endif
REG32(ZDMA_ERR_CTRL, 0x0)
FIELD(ZDMA_ERR_CTRL, APB_ERR_RES, 0, 1)
REG32(ZDMA_CH_ISR, 0x100)
FIELD(ZDMA_CH_ISR, DMA_PAUSE, 11, 1)
FIELD(ZDMA_CH_ISR, DMA_DONE, 10, 1)
FIELD(ZDMA_CH_ISR, AXI_WR_DATA, 9, 1)
FIELD(ZDMA_CH_ISR, AXI_RD_DATA, 8, 1)
FIELD(ZDMA_CH_ISR, AXI_RD_DST_DSCR, 7, 1)
FIELD(ZDMA_CH_ISR, AXI_RD_SRC_DSCR, 6, 1)
FIELD(ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, 5, 1)
FIELD(ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, 4, 1)
FIELD(ZDMA_CH_ISR, BYTE_CNT_OVRFL, 3, 1)
FIELD(ZDMA_CH_ISR, DST_DSCR_DONE, 2, 1)
FIELD(ZDMA_CH_ISR, SRC_DSCR_DONE, 1, 1)
FIELD(ZDMA_CH_ISR, INV_APB, 0, 1)
REG32(ZDMA_CH_IMR, 0x104)
FIELD(ZDMA_CH_IMR, DMA_PAUSE, 11, 1)
FIELD(ZDMA_CH_IMR, DMA_DONE, 10, 1)
FIELD(ZDMA_CH_IMR, AXI_WR_DATA, 9, 1)
FIELD(ZDMA_CH_IMR, AXI_RD_DATA, 8, 1)
FIELD(ZDMA_CH_IMR, AXI_RD_DST_DSCR, 7, 1)
FIELD(ZDMA_CH_IMR, AXI_RD_SRC_DSCR, 6, 1)
FIELD(ZDMA_CH_IMR, IRQ_DST_ACCT_ERR, 5, 1)
FIELD(ZDMA_CH_IMR, IRQ_SRC_ACCT_ERR, 4, 1)
FIELD(ZDMA_CH_IMR, BYTE_CNT_OVRFL, 3, 1)
FIELD(ZDMA_CH_IMR, DST_DSCR_DONE, 2, 1)
FIELD(ZDMA_CH_IMR, SRC_DSCR_DONE, 1, 1)
FIELD(ZDMA_CH_IMR, INV_APB, 0, 1)
REG32(ZDMA_CH_IEN, 0x108)
FIELD(ZDMA_CH_IEN, DMA_PAUSE, 11, 1)
FIELD(ZDMA_CH_IEN, DMA_DONE, 10, 1)
FIELD(ZDMA_CH_IEN, AXI_WR_DATA, 9, 1)
FIELD(ZDMA_CH_IEN, AXI_RD_DATA, 8, 1)
FIELD(ZDMA_CH_IEN, AXI_RD_DST_DSCR, 7, 1)
FIELD(ZDMA_CH_IEN, AXI_RD_SRC_DSCR, 6, 1)
FIELD(ZDMA_CH_IEN, IRQ_DST_ACCT_ERR, 5, 1)
FIELD(ZDMA_CH_IEN, IRQ_SRC_ACCT_ERR, 4, 1)
FIELD(ZDMA_CH_IEN, BYTE_CNT_OVRFL, 3, 1)
FIELD(ZDMA_CH_IEN, DST_DSCR_DONE, 2, 1)
FIELD(ZDMA_CH_IEN, SRC_DSCR_DONE, 1, 1)
FIELD(ZDMA_CH_IEN, INV_APB, 0, 1)
REG32(ZDMA_CH_IDS, 0x10c)
FIELD(ZDMA_CH_IDS, DMA_PAUSE, 11, 1)
FIELD(ZDMA_CH_IDS, DMA_DONE, 10, 1)
FIELD(ZDMA_CH_IDS, AXI_WR_DATA, 9, 1)
FIELD(ZDMA_CH_IDS, AXI_RD_DATA, 8, 1)
FIELD(ZDMA_CH_IDS, AXI_RD_DST_DSCR, 7, 1)
FIELD(ZDMA_CH_IDS, AXI_RD_SRC_DSCR, 6, 1)
FIELD(ZDMA_CH_IDS, IRQ_DST_ACCT_ERR, 5, 1)
FIELD(ZDMA_CH_IDS, IRQ_SRC_ACCT_ERR, 4, 1)
FIELD(ZDMA_CH_IDS, BYTE_CNT_OVRFL, 3, 1)
FIELD(ZDMA_CH_IDS, DST_DSCR_DONE, 2, 1)
FIELD(ZDMA_CH_IDS, SRC_DSCR_DONE, 1, 1)
FIELD(ZDMA_CH_IDS, INV_APB, 0, 1)
REG32(ZDMA_CH_CTRL0, 0x110)
FIELD(ZDMA_CH_CTRL0, OVR_FETCH, 7, 1)
FIELD(ZDMA_CH_CTRL0, POINT_TYPE, 6, 1)
FIELD(ZDMA_CH_CTRL0, MODE, 4, 2)
FIELD(ZDMA_CH_CTRL0, RATE_CTRL, 3, 1)
FIELD(ZDMA_CH_CTRL0, CONT_ADDR, 2, 1)
FIELD(ZDMA_CH_CTRL0, CONT, 1, 1)
REG32(ZDMA_CH_CTRL1, 0x114)
FIELD(ZDMA_CH_CTRL1, DST_ISSUE, 5, 5)
FIELD(ZDMA_CH_CTRL1, SRC_ISSUE, 0, 5)
REG32(ZDMA_CH_FCI, 0x118)
FIELD(ZDMA_CH_FCI, PROG_CELL_CNT, 2, 2)
FIELD(ZDMA_CH_FCI, SIDE, 1, 1)
FIELD(ZDMA_CH_FCI, EN, 0, 1)
REG32(ZDMA_CH_STATUS, 0x11c)
FIELD(ZDMA_CH_STATUS, STATE, 0, 2)
REG32(ZDMA_CH_DATA_ATTR, 0x120)
FIELD(ZDMA_CH_DATA_ATTR, ARBURST, 26, 2)
FIELD(ZDMA_CH_DATA_ATTR, ARCACHE, 22, 4)
FIELD(ZDMA_CH_DATA_ATTR, ARQOS, 18, 4)
FIELD(ZDMA_CH_DATA_ATTR, ARLEN, 14, 4)
FIELD(ZDMA_CH_DATA_ATTR, AWBURST, 12, 2)
FIELD(ZDMA_CH_DATA_ATTR, AWCACHE, 8, 4)
FIELD(ZDMA_CH_DATA_ATTR, AWQOS, 4, 4)
FIELD(ZDMA_CH_DATA_ATTR, AWLEN, 0, 4)
REG32(ZDMA_CH_DSCR_ATTR, 0x124)
FIELD(ZDMA_CH_DSCR_ATTR, AXCOHRNT, 8, 1)
FIELD(ZDMA_CH_DSCR_ATTR, AXCACHE, 4, 4)
FIELD(ZDMA_CH_DSCR_ATTR, AXQOS, 0, 4)
REG32(ZDMA_CH_SRC_DSCR_WORD0, 0x128)
REG32(ZDMA_CH_SRC_DSCR_WORD1, 0x12c)
FIELD(ZDMA_CH_SRC_DSCR_WORD1, MSB, 0, 17)
REG32(ZDMA_CH_SRC_DSCR_WORD2, 0x130)
FIELD(ZDMA_CH_SRC_DSCR_WORD2, SIZE, 0, 30)
REG32(ZDMA_CH_SRC_DSCR_WORD3, 0x134)
FIELD(ZDMA_CH_SRC_DSCR_WORD3, CMD, 3, 2)
FIELD(ZDMA_CH_SRC_DSCR_WORD3, INTR, 2, 1)
FIELD(ZDMA_CH_SRC_DSCR_WORD3, TYPE, 1, 1)
FIELD(ZDMA_CH_SRC_DSCR_WORD3, COHRNT, 0, 1)
REG32(ZDMA_CH_DST_DSCR_WORD0, 0x138)
REG32(ZDMA_CH_DST_DSCR_WORD1, 0x13c)
FIELD(ZDMA_CH_DST_DSCR_WORD1, MSB, 0, 17)
REG32(ZDMA_CH_DST_DSCR_WORD2, 0x140)
FIELD(ZDMA_CH_DST_DSCR_WORD2, SIZE, 0, 30)
REG32(ZDMA_CH_DST_DSCR_WORD3, 0x144)
FIELD(ZDMA_CH_DST_DSCR_WORD3, INTR, 2, 1)
FIELD(ZDMA_CH_DST_DSCR_WORD3, TYPE, 1, 1)
FIELD(ZDMA_CH_DST_DSCR_WORD3, COHRNT, 0, 1)
REG32(ZDMA_CH_WR_ONLY_WORD0, 0x148)
REG32(ZDMA_CH_WR_ONLY_WORD1, 0x14c)
REG32(ZDMA_CH_WR_ONLY_WORD2, 0x150)
REG32(ZDMA_CH_WR_ONLY_WORD3, 0x154)
REG32(ZDMA_CH_SRC_START_LSB, 0x158)
REG32(ZDMA_CH_SRC_START_MSB, 0x15c)
FIELD(ZDMA_CH_SRC_START_MSB, ADDR, 0, 17)
REG32(ZDMA_CH_DST_START_LSB, 0x160)
REG32(ZDMA_CH_DST_START_MSB, 0x164)
FIELD(ZDMA_CH_DST_START_MSB, ADDR, 0, 17)
REG32(ZDMA_CH_RATE_CTRL, 0x18c)
FIELD(ZDMA_CH_RATE_CTRL, CNT, 0, 12)
REG32(ZDMA_CH_SRC_CUR_PYLD_LSB, 0x168)
REG32(ZDMA_CH_SRC_CUR_PYLD_MSB, 0x16c)
FIELD(ZDMA_CH_SRC_CUR_PYLD_MSB, ADDR, 0, 17)
REG32(ZDMA_CH_DST_CUR_PYLD_LSB, 0x170)
REG32(ZDMA_CH_DST_CUR_PYLD_MSB, 0x174)
FIELD(ZDMA_CH_DST_CUR_PYLD_MSB, ADDR, 0, 17)
REG32(ZDMA_CH_SRC_CUR_DSCR_LSB, 0x178)
REG32(ZDMA_CH_SRC_CUR_DSCR_MSB, 0x17c)
FIELD(ZDMA_CH_SRC_CUR_DSCR_MSB, ADDR, 0, 17)
REG32(ZDMA_CH_DST_CUR_DSCR_LSB, 0x180)
REG32(ZDMA_CH_DST_CUR_DSCR_MSB, 0x184)
FIELD(ZDMA_CH_DST_CUR_DSCR_MSB, ADDR, 0, 17)
REG32(ZDMA_CH_TOTAL_BYTE, 0x188)
REG32(ZDMA_CH_RATE_CNTL, 0x18c)
FIELD(ZDMA_CH_RATE_CNTL, CNT, 0, 12)
REG32(ZDMA_CH_IRQ_SRC_ACCT, 0x190)
FIELD(ZDMA_CH_IRQ_SRC_ACCT, CNT, 0, 8)
REG32(ZDMA_CH_IRQ_DST_ACCT, 0x194)
FIELD(ZDMA_CH_IRQ_DST_ACCT, CNT, 0, 8)
REG32(ZDMA_CH_DBG0, 0x198)
FIELD(ZDMA_CH_DBG0, CMN_BUF_FREE, 0, 9)
REG32(ZDMA_CH_DBG1, 0x19c)
FIELD(ZDMA_CH_DBG1, CMN_BUF_OCC, 0, 9)
REG32(ZDMA_CH_CTRL2, 0x200)
FIELD(ZDMA_CH_CTRL2, EN, 0, 1)
enum {
PT_REG = 0,
PT_MEM = 1,
};
enum {
CMD_HALT = 1,
CMD_STOP = 2,
};
enum {
RW_MODE_RW = 0,
RW_MODE_WO = 1,
RW_MODE_RO = 2,
};
enum {
DTYPE_LINEAR = 0,
DTYPE_LINKED = 1,
};
enum {
AXI_BURST_FIXED = 0,
AXI_BURST_INCR = 1,
};
static void zdma_ch_imr_update_irq(XlnxZDMA *s)
{
bool pending;
pending = s->regs[R_ZDMA_CH_ISR] & ~s->regs[R_ZDMA_CH_IMR];
qemu_set_irq(s->irq_zdma_ch_imr, pending);
}
static void zdma_ch_isr_postw(RegisterInfo *reg, uint64_t val64)
{
XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
zdma_ch_imr_update_irq(s);
}
static uint64_t zdma_ch_ien_prew(RegisterInfo *reg, uint64_t val64)
{
XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
uint32_t val = val64;
s->regs[R_ZDMA_CH_IMR] &= ~val;
zdma_ch_imr_update_irq(s);
return 0;
}
static uint64_t zdma_ch_ids_prew(RegisterInfo *reg, uint64_t val64)
{
XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
uint32_t val = val64;
s->regs[R_ZDMA_CH_IMR] |= val;
zdma_ch_imr_update_irq(s);
return 0;
}
static void zdma_set_state(XlnxZDMA *s, XlnxZDMAState state)
{
s->state = state;
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, state);
/* Signal error if we have an error condition. */
if (s->error) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, 3);
}
}
static void zdma_src_done(XlnxZDMA *s)
{
unsigned int cnt;
cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT);
cnt++;
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT, cnt);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, SRC_DSCR_DONE, true);
/* Did we overflow? */
if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT)) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, true);
}
zdma_ch_imr_update_irq(s);
}
static void zdma_dst_done(XlnxZDMA *s)
{
unsigned int cnt;
cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT);
cnt++;
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT, cnt);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DST_DSCR_DONE, true);
/* Did we overflow? */
if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT)) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, true);
}
zdma_ch_imr_update_irq(s);
}
static uint64_t zdma_get_regaddr64(XlnxZDMA *s, unsigned int basereg)
{
uint64_t addr;
addr = s->regs[basereg + 1];
addr <<= 32;
addr |= s->regs[basereg];
return addr;
}
static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
{
s->regs[basereg] = addr;
s->regs[basereg + 1] = addr >> 32;
}
static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
{
/* ZDMA descriptors must be aligned to their own size. */
if (addr % sizeof(XlnxZDMADescr)) {
qemu_log_mask(LOG_GUEST_ERROR,
"zdma: unaligned descriptor at %" PRIx64,
addr);
memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
s->error = true;
return false;
}
address_space_rw(s->dma_as, addr, s->attr,
buf, sizeof(XlnxZDMADescr), false);
return true;
}
static void zdma_load_src_descriptor(XlnxZDMA *s)
{
uint64_t src_addr;
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
if (ptype == PT_REG) {
memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0],
sizeof(s->dsc_src));
return;
}
src_addr = zdma_get_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB);
if (!zdma_load_descriptor(s, src_addr, &s->dsc_src)) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_SRC_DSCR, true);
}
}
static void zdma_load_dst_descriptor(XlnxZDMA *s)
{
uint64_t dst_addr;
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
if (ptype == PT_REG) {
memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0],
sizeof(s->dsc_dst));
return;
}
dst_addr = zdma_get_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB);
if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true);
}
}
static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type,
unsigned int basereg)
{
uint64_t addr, next;
if (type == DTYPE_LINEAR) {
next = zdma_get_regaddr64(s, basereg);
next += sizeof(s->dsc_dst);
zdma_put_regaddr64(s, basereg, next);
} else {
addr = zdma_get_regaddr64(s, basereg);
addr += sizeof(s->dsc_dst);
address_space_rw(s->dma_as, addr, s->attr, (void *) &next, 8, false);
zdma_put_regaddr64(s, basereg, next);
}
return next;
}
static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
{
uint32_t dst_size, dlen;
bool dst_intr, dst_type;
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE);
unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR,
AWBURST);
/* FIXED burst types are only supported in simple dma mode. */
if (ptype != PT_REG) {
burst_type = AXI_BURST_INCR;
}
while (len) {
dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
SIZE);
dst_type = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3,
TYPE);
if (dst_size == 0 && ptype == PT_MEM) {
uint64_t next;
next = zdma_update_descr_addr(s, dst_type,
R_ZDMA_CH_DST_CUR_DSCR_LSB);
zdma_load_descriptor(s, next, &s->dsc_dst);
dst_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
SIZE);
dst_type = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3,
TYPE);
}
/* Match what hardware does by ignoring the dst_size and only using
* the src size for Simple register mode. */
if (ptype == PT_REG && rw_mode != RW_MODE_WO) {
dst_size = len;
}
dst_intr = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3,
INTR);
dlen = len > dst_size ? dst_size : len;
if (burst_type == AXI_BURST_FIXED) {
if (dlen > (s->cfg.bus_width / 8)) {
dlen = s->cfg.bus_width / 8;
}
}
address_space_rw(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen,
true);
if (burst_type == AXI_BURST_INCR) {
s->dsc_dst.addr += dlen;
}
dst_size -= dlen;
buf += dlen;
len -= dlen;
if (dst_size == 0 && dst_intr) {
zdma_dst_done(s);
}
/* Write back to buffered descriptor. */
s->dsc_dst.words[2] = FIELD_DP32(s->dsc_dst.words[2],
ZDMA_CH_DST_DSCR_WORD2,
SIZE,
dst_size);
}
}
static void zdma_process_descr(XlnxZDMA *s)
{
uint64_t src_addr;
uint32_t src_size, len;
unsigned int src_cmd;
bool src_intr, src_type;
unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE);
unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE);
unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR,
ARBURST);
src_addr = s->dsc_src.addr;
src_size = FIELD_EX32(s->dsc_src.words[2], ZDMA_CH_SRC_DSCR_WORD2, SIZE);
src_cmd = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, CMD);
src_type = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, TYPE);
src_intr = FIELD_EX32(s->dsc_src.words[3], ZDMA_CH_SRC_DSCR_WORD3, INTR);
/* FIXED burst types and non-rw modes are only supported in
* simple dma mode.
*/
if (ptype != PT_REG) {
if (rw_mode != RW_MODE_RW) {
qemu_log_mask(LOG_GUEST_ERROR,
"zDMA: rw-mode=%d but not simple DMA mode.\n",
rw_mode);
}
if (burst_type != AXI_BURST_INCR) {
qemu_log_mask(LOG_GUEST_ERROR,
"zDMA: burst_type=%d but not simple DMA mode.\n",
burst_type);
}
burst_type = AXI_BURST_INCR;
rw_mode = RW_MODE_RW;
}
if (rw_mode == RW_MODE_WO) {
/* In Simple DMA Write-Only, we need to push DST size bytes
* regardless of what SRC size is set to. */
src_size = FIELD_EX32(s->dsc_dst.words[2], ZDMA_CH_DST_DSCR_WORD2,
SIZE);
memcpy(s->buf, &s->regs[R_ZDMA_CH_WR_ONLY_WORD0], s->cfg.bus_width / 8);
}
while (src_size) {
len = src_size > ARRAY_SIZE(s->buf) ? ARRAY_SIZE(s->buf) : src_size;
if (burst_type == AXI_BURST_FIXED) {
if (len > (s->cfg.bus_width / 8)) {
len = s->cfg.bus_width / 8;
}
}
if (rw_mode == RW_MODE_WO) {
if (len > s->cfg.bus_width / 8) {
len = s->cfg.bus_width / 8;
}
} else {
address_space_rw(s->dma_as, src_addr, s->attr, s->buf, len,
false);
if (burst_type == AXI_BURST_INCR) {
src_addr += len;
}
}
if (rw_mode != RW_MODE_RO) {
zdma_write_dst(s, s->buf, len);
}
s->regs[R_ZDMA_CH_TOTAL_BYTE] += len;
src_size -= len;
}
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_DONE, true);
if (src_intr) {
zdma_src_done(s);
}
/* Load next descriptor. */
if (ptype == PT_REG || src_cmd == CMD_STOP) {
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL2, EN, 0);
zdma_set_state(s, DISABLED);
return;
}
if (src_cmd == CMD_HALT) {
zdma_set_state(s, PAUSED);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DMA_PAUSE, 1);
zdma_ch_imr_update_irq(s);
return;
}
zdma_update_descr_addr(s, src_type, R_ZDMA_CH_SRC_CUR_DSCR_LSB);
}
static void zdma_run(XlnxZDMA *s)
{
while (s->state == ENABLED && !s->error) {
zdma_load_src_descriptor(s);
if (s->error) {
zdma_set_state(s, DISABLED);
} else {
zdma_process_descr(s);
}
}
zdma_ch_imr_update_irq(s);
}
static void zdma_update_descr_addr_from_start(XlnxZDMA *s)
{
uint64_t src_addr, dst_addr;
src_addr = zdma_get_regaddr64(s, R_ZDMA_CH_SRC_START_LSB);
zdma_put_regaddr64(s, R_ZDMA_CH_SRC_CUR_DSCR_LSB, src_addr);
dst_addr = zdma_get_regaddr64(s, R_ZDMA_CH_DST_START_LSB);
zdma_put_regaddr64(s, R_ZDMA_CH_DST_CUR_DSCR_LSB, dst_addr);
zdma_load_dst_descriptor(s);
}
static void zdma_ch_ctrlx_postw(RegisterInfo *reg, uint64_t val64)
{
XlnxZDMA *s = XLNX_ZDMA(reg->opaque);
if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL2, EN)) {
s->error = false;
if (s->state == PAUSED &&
ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) {
if (ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT_ADDR) == 1) {
zdma_update_descr_addr_from_start(s);
} else {
bool src_type = FIELD_EX32(s->dsc_src.words[3],
ZDMA_CH_SRC_DSCR_WORD3, TYPE);
zdma_update_descr_addr(s, src_type,
R_ZDMA_CH_SRC_CUR_DSCR_LSB);
}
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_CTRL0, CONT, false);
zdma_set_state(s, ENABLED);
} else if (s->state == DISABLED) {
zdma_update_descr_addr_from_start(s);
zdma_set_state(s, ENABLED);
}
} else {
/* Leave Paused state? */
if (s->state == PAUSED &&
ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, CONT)) {
zdma_set_state(s, DISABLED);
}
}
zdma_run(s);
}
static RegisterAccessInfo zdma_regs_info[] = {
{ .name = "ZDMA_ERR_CTRL", .addr = A_ZDMA_ERR_CTRL,
.rsvd = 0xfffffffe,
},{ .name = "ZDMA_CH_ISR", .addr = A_ZDMA_CH_ISR,
.rsvd = 0xfffff000,
.w1c = 0xfff,
.post_write = zdma_ch_isr_postw,
},{ .name = "ZDMA_CH_IMR", .addr = A_ZDMA_CH_IMR,
.reset = 0xfff,
.rsvd = 0xfffff000,
.ro = 0xfff,
},{ .name = "ZDMA_CH_IEN", .addr = A_ZDMA_CH_IEN,
.rsvd = 0xfffff000,
.pre_write = zdma_ch_ien_prew,
},{ .name = "ZDMA_CH_IDS", .addr = A_ZDMA_CH_IDS,
.rsvd = 0xfffff000,
.pre_write = zdma_ch_ids_prew,
},{ .name = "ZDMA_CH_CTRL0", .addr = A_ZDMA_CH_CTRL0,
.reset = 0x80,
.rsvd = 0xffffff01,
.post_write = zdma_ch_ctrlx_postw,
},{ .name = "ZDMA_CH_CTRL1", .addr = A_ZDMA_CH_CTRL1,
.reset = 0x3ff,
.rsvd = 0xfffffc00,
},{ .name = "ZDMA_CH_FCI", .addr = A_ZDMA_CH_FCI,
.rsvd = 0xffffffc0,
},{ .name = "ZDMA_CH_STATUS", .addr = A_ZDMA_CH_STATUS,
.rsvd = 0xfffffffc,
.ro = 0x3,
},{ .name = "ZDMA_CH_DATA_ATTR", .addr = A_ZDMA_CH_DATA_ATTR,
.reset = 0x483d20f,
.rsvd = 0xf0000000,
},{ .name = "ZDMA_CH_DSCR_ATTR", .addr = A_ZDMA_CH_DSCR_ATTR,
.rsvd = 0xfffffe00,
},{ .name = "ZDMA_CH_SRC_DSCR_WORD0", .addr = A_ZDMA_CH_SRC_DSCR_WORD0,
},{ .name = "ZDMA_CH_SRC_DSCR_WORD1", .addr = A_ZDMA_CH_SRC_DSCR_WORD1,
.rsvd = 0xfffe0000,
},{ .name = "ZDMA_CH_SRC_DSCR_WORD2", .addr = A_ZDMA_CH_SRC_DSCR_WORD2,
.rsvd = 0xc0000000,
},{ .name = "ZDMA_CH_SRC_DSCR_WORD3", .addr = A_ZDMA_CH_SRC_DSCR_WORD3,
.rsvd = 0xffffffe0,
},{ .name = "ZDMA_CH_DST_DSCR_WORD0", .addr = A_ZDMA_CH_DST_DSCR_WORD0,
},{ .name = "ZDMA_CH_DST_DSCR_WORD1", .addr = A_ZDMA_CH_DST_DSCR_WORD1,
.rsvd = 0xfffe0000,
},{ .name = "ZDMA_CH_DST_DSCR_WORD2", .addr = A_ZDMA_CH_DST_DSCR_WORD2,
.rsvd = 0xc0000000,
},{ .name = "ZDMA_CH_DST_DSCR_WORD3", .addr = A_ZDMA_CH_DST_DSCR_WORD3,
.rsvd = 0xfffffffa,
},{ .name = "ZDMA_CH_WR_ONLY_WORD0", .addr = A_ZDMA_CH_WR_ONLY_WORD0,
},{ .name = "ZDMA_CH_WR_ONLY_WORD1", .addr = A_ZDMA_CH_WR_ONLY_WORD1,
},{ .name = "ZDMA_CH_WR_ONLY_WORD2", .addr = A_ZDMA_CH_WR_ONLY_WORD2,
},{ .name = "ZDMA_CH_WR_ONLY_WORD3", .addr = A_ZDMA_CH_WR_ONLY_WORD3,
},{ .name = "ZDMA_CH_SRC_START_LSB", .addr = A_ZDMA_CH_SRC_START_LSB,
},{ .name = "ZDMA_CH_SRC_START_MSB", .addr = A_ZDMA_CH_SRC_START_MSB,
.rsvd = 0xfffe0000,
},{ .name = "ZDMA_CH_DST_START_LSB", .addr = A_ZDMA_CH_DST_START_LSB,
},{ .name = "ZDMA_CH_DST_START_MSB", .addr = A_ZDMA_CH_DST_START_MSB,
.rsvd = 0xfffe0000,
},{ .name = "ZDMA_CH_SRC_CUR_PYLD_LSB", .addr = A_ZDMA_CH_SRC_CUR_PYLD_LSB,
.ro = 0xffffffff,
},{ .name = "ZDMA_CH_SRC_CUR_PYLD_MSB", .addr = A_ZDMA_CH_SRC_CUR_PYLD_MSB,
.rsvd = 0xfffe0000,
.ro = 0x1ffff,
},{ .name = "ZDMA_CH_DST_CUR_PYLD_LSB", .addr = A_ZDMA_CH_DST_CUR_PYLD_LSB,
.ro = 0xffffffff,
},{ .name = "ZDMA_CH_DST_CUR_PYLD_MSB", .addr = A_ZDMA_CH_DST_CUR_PYLD_MSB,
.rsvd = 0xfffe0000,
.ro = 0x1ffff,
},{ .name = "ZDMA_CH_SRC_CUR_DSCR_LSB", .addr = A_ZDMA_CH_SRC_CUR_DSCR_LSB,
.ro = 0xffffffff,
},{ .name = "ZDMA_CH_SRC_CUR_DSCR_MSB", .addr = A_ZDMA_CH_SRC_CUR_DSCR_MSB,
.rsvd = 0xfffe0000,
.ro = 0x1ffff,
},{ .name = "ZDMA_CH_DST_CUR_DSCR_LSB", .addr = A_ZDMA_CH_DST_CUR_DSCR_LSB,
.ro = 0xffffffff,
},{ .name = "ZDMA_CH_DST_CUR_DSCR_MSB", .addr = A_ZDMA_CH_DST_CUR_DSCR_MSB,
.rsvd = 0xfffe0000,
.ro = 0x1ffff,
},{ .name = "ZDMA_CH_TOTAL_BYTE", .addr = A_ZDMA_CH_TOTAL_BYTE,
.w1c = 0xffffffff,
},{ .name = "ZDMA_CH_RATE_CNTL", .addr = A_ZDMA_CH_RATE_CNTL,
.rsvd = 0xfffff000,
},{ .name = "ZDMA_CH_IRQ_SRC_ACCT", .addr = A_ZDMA_CH_IRQ_SRC_ACCT,
.rsvd = 0xffffff00,
.ro = 0xff,
.cor = 0xff,
},{ .name = "ZDMA_CH_IRQ_DST_ACCT", .addr = A_ZDMA_CH_IRQ_DST_ACCT,
.rsvd = 0xffffff00,
.ro = 0xff,
.cor = 0xff,
},{ .name = "ZDMA_CH_DBG0", .addr = A_ZDMA_CH_DBG0,
.rsvd = 0xfffffe00,
.ro = 0x1ff,
},{ .name = "ZDMA_CH_DBG1", .addr = A_ZDMA_CH_DBG1,
.rsvd = 0xfffffe00,
.ro = 0x1ff,
},{ .name = "ZDMA_CH_CTRL2", .addr = A_ZDMA_CH_CTRL2,
.rsvd = 0xfffffffe,
.post_write = zdma_ch_ctrlx_postw,
}
};
static void zdma_reset(DeviceState *dev)
{
XlnxZDMA *s = XLNX_ZDMA(dev);
unsigned int i;
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
register_reset(&s->regs_info[i]);
}
zdma_ch_imr_update_irq(s);
}
static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
{
XlnxZDMA *s = XLNX_ZDMA(opaque);
RegisterInfo *r = &s->regs_info[addr / 4];
if (!r->data) {
qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
object_get_canonical_path(OBJECT(s)),
addr);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
zdma_ch_imr_update_irq(s);
return 0;
}
return register_read(r, ~0, NULL, false);
}
static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
XlnxZDMA *s = XLNX_ZDMA(opaque);
RegisterInfo *r = &s->regs_info[addr / 4];
if (!r->data) {
qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
object_get_canonical_path(OBJECT(s)),
addr, value);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
zdma_ch_imr_update_irq(s);
return;
}
register_write(r, value, ~0, NULL, false);
}
static const MemoryRegionOps zdma_ops = {
.read = zdma_read,
.write = zdma_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void zdma_realize(DeviceState *dev, Error **errp)
{
XlnxZDMA *s = XLNX_ZDMA(dev);
unsigned int i;
for (i = 0; i < ARRAY_SIZE(zdma_regs_info); ++i) {
RegisterInfo *r = &s->regs_info[zdma_regs_info[i].addr / 4];
*r = (RegisterInfo) {
.data = (uint8_t *)&s->regs[
zdma_regs_info[i].addr / 4],
.data_size = sizeof(uint32_t),
.access = &zdma_regs_info[i],
.opaque = s,
};
}
if (s->dma_mr) {
s->dma_as = g_malloc0(sizeof(AddressSpace));
address_space_init(s->dma_as, s->dma_mr, NULL);
} else {
s->dma_as = &address_space_memory;
}
s->attr = MEMTXATTRS_UNSPECIFIED;
}
static void zdma_init(Object *obj)
{
XlnxZDMA *s = XLNX_ZDMA(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &zdma_ops, s,
TYPE_XLNX_ZDMA, ZDMA_R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq_zdma_ch_imr);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->dma_mr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
}
static const VMStateDescription vmstate_zdma = {
.name = TYPE_XLNX_ZDMA,
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, XlnxZDMA, ZDMA_R_MAX),
VMSTATE_UINT32(state, XlnxZDMA),
VMSTATE_UINT32_ARRAY(dsc_src.words, XlnxZDMA, 4),
VMSTATE_UINT32_ARRAY(dsc_dst.words, XlnxZDMA, 4),
VMSTATE_END_OF_LIST(),
}
};
static Property zdma_props[] = {
DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64),
DEFINE_PROP_END_OF_LIST(),
};
static void zdma_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = zdma_reset;
dc->realize = zdma_realize;
dc->props = zdma_props;
dc->vmsd = &vmstate_zdma;
}
static const TypeInfo zdma_info = {
.name = TYPE_XLNX_ZDMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(XlnxZDMA),
.class_init = zdma_class_init,
.instance_init = zdma_init,
};
static void zdma_register_types(void)
{
type_register_static(&zdma_info);
}
type_init(zdma_register_types)

5
include/hw/arm/xlnx-zynqmp.h
View File

@ -27,6 +27,7 @@
#include "hw/sd/sdhci.h"
#include "hw/ssi/xilinx_spips.h"
#include "hw/dma/xlnx_dpdma.h"
#include "hw/dma/xlnx-zdma.h"
#include "hw/display/xlnx_dp.h"
#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/timer/xlnx-zynqmp-rtc.h"
@ -41,6 +42,8 @@
#define XLNX_ZYNQMP_NUM_UARTS 2
#define XLNX_ZYNQMP_NUM_SDHCI 2
#define XLNX_ZYNQMP_NUM_SPIS 2
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
@ -94,6 +97,8 @@ typedef struct XlnxZynqMPState {
XlnxDPDMAState dpdma;
XlnxZynqMPIPI ipi;
XlnxZynqMPRTC rtc;
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
char *boot_cpu;
ARMCPU *boot_cpu_ptr;

84
include/hw/dma/xlnx-zdma.h Normal file
View File

@ -0,0 +1,84 @@
/*
* QEMU model of the ZynqMP generic DMA
*
* Copyright (c) 2014 Xilinx Inc.
* Copyright (c) 2018 FEIMTECH AB
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>,
* Francisco Iglesias <francisco.iglesias@feimtech.se>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef XLNX_ZDMA_H
#define XLNX_ZDMA_H
#include "hw/sysbus.h"
#include "hw/register.h"
#include "sysemu/dma.h"
#define ZDMA_R_MAX (0x204 / 4)
typedef enum {
DISABLED = 0,
ENABLED = 1,
PAUSED = 2,
} XlnxZDMAState;
typedef union {
struct {
uint64_t addr;
uint32_t size;
uint32_t attr;
};
uint32_t words[4];
} XlnxZDMADescr;
typedef struct XlnxZDMA {
SysBusDevice parent_obj;
MemoryRegion iomem;
MemTxAttrs attr;
MemoryRegion *dma_mr;
AddressSpace *dma_as;
qemu_irq irq_zdma_ch_imr;
struct {
uint32_t bus_width;
} cfg;
XlnxZDMAState state;
bool error;
XlnxZDMADescr dsc_src;
XlnxZDMADescr dsc_dst;
uint32_t regs[ZDMA_R_MAX];
RegisterInfo regs_info[ZDMA_R_MAX];
/* We don't model the common bufs. Must be at least 16 bytes
to model write only mode. */
uint8_t buf[2048];
} XlnxZDMA;
#define TYPE_XLNX_ZDMA "xlnx.zdma"
#define XLNX_ZDMA(obj) \
OBJECT_CHECK(XlnxZDMA, (obj), TYPE_XLNX_ZDMA)
#endif /* XLNX_ZDMA_H */

5
include/qom/cpu.h
View File

@ -132,6 +132,9 @@ struct TranslationBlock;
* before the insn which triggers a watchpoint rather than after it.
* @gdb_arch_name: Optional callback that returns the architecture name known
* to GDB. The caller must free the returned string with g_free.
* @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
* gdb stub. Returns a pointer to the XML contents for the specified XML file
* or NULL if the CPU doesn't have a dynamically generated content for it.
* @cpu_exec_enter: Callback for cpu_exec preparation.
* @cpu_exec_exit: Callback for cpu_exec cleanup.
* @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
@ -198,7 +201,7 @@ typedef struct CPUClass {
const struct VMStateDescription *vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
void (*cpu_exec_enter)(CPUState *cpu);
void (*cpu_exec_exit)(CPUState *cpu);
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);

10
target/arm/Makefile.objs
View File

@ -10,3 +10,13 @@ obj-y += gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
obj-y += crypto_helper.o
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
target/arm/translate-sve.o: target/arm/decode-sve.inc.c
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o

1
target/arm/cpu.c
View File

@ -1908,6 +1908,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
cc->gdb_arch_name = arm_gdb_arch_name;
cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;

37
target/arm/cpu.h
View File

@ -133,6 +133,19 @@ enum {
s<2n+1> maps to the most significant half of d<n>
*/
/**
* DynamicGDBXMLInfo:
* @desc: Contains the XML descriptions.
* @num_cpregs: Number of the Coprocessor registers seen by GDB.
* @cpregs_keys: Array that contains the corresponding Key of
* a given cpreg with the same order of the cpreg in the XML description.
*/
typedef struct DynamicGDBXMLInfo {
char *desc;
int num_cpregs;
uint32_t *cpregs_keys;
} DynamicGDBXMLInfo;
/* CPU state for each instance of a generic timer (in cp15 c14) */
typedef struct ARMGenericTimer {
uint64_t cval; /* Timer CompareValue register */
@ -527,7 +540,10 @@ typedef struct CPUARMState {
#ifdef TARGET_AARCH64
/* Store FFR as pregs[16] to make it easier to treat as any other. */
#define FFR_PRED_NUM 16
ARMPredicateReg pregs[17];
/* Scratch space for aa64 sve predicate temporary. */
ARMPredicateReg preg_tmp;
#endif
uint32_t xregs[16];
@ -535,7 +551,7 @@ typedef struct CPUARMState {
int vec_len;
int vec_stride;
/* scratch space when Tn are not sufficient. */
/* Scratch space for aa32 neon expansion. */
uint32_t scratch[8];
/* There are a number of distinct float control structures:
@ -687,6 +703,8 @@ struct ARMCPU {
uint64_t *cpreg_vmstate_values;
int32_t cpreg_vmstate_array_len;
DynamicGDBXMLInfo dyn_xml;
/* Timers used by the generic (architected) timer */
QEMUTimer *gt_timer[NUM_GTIMERS];
/* GPIO outputs for generic timer */
@ -868,6 +886,17 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
/* Dynamically generates for gdb stub an XML description of the sysregs from
* the cp_regs hashtable. Returns the registered sysregs number.
*/
int arm_gen_dynamic_xml(CPUState *cpu);
/* Returns the dynamically generated XML for the gdb stub.
* Returns a pointer to the XML contents for the specified XML file or NULL
* if the XML name doesn't match the predefined one.
*/
const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
@ -1821,10 +1850,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
#define ARM_CP_FPU 0x1000
#define ARM_CP_SVE 0x2000
#define ARM_CP_NO_GDB 0x4000
/* Used only as a terminator for ARMCPRegInfo lists */
#define ARM_CP_SENTINEL 0xffff
/* Mask of only the flag bits in a type field */
#define ARM_CP_FLAG_MASK 0x30ff
#define ARM_CP_FLAG_MASK 0x70ff
/* Valid values for ARMCPRegInfo state field, indicating which of
* the AArch32 and AArch64 execution states this register is visible in.
@ -2946,4 +2976,7 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
return &env->vfp.zregs[regno].d[0];
}
/* Shared between translate-sve.c and sve_helper.c. */
extern const uint64_t pred_esz_masks[4];
#endif

76
target/arm/gdbstub.c
View File

@ -22,6 +22,11 @@
#include "cpu.h"
#include "exec/gdbstub.h"
typedef struct RegisterSysregXmlParam {
CPUState *cs;
GString *s;
} RegisterSysregXmlParam;
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
whatever the target description contains. Due to a historical mishap
the FPA registers appear in between core integer regs and the CPSR.
@ -101,3 +106,74 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
/* Unknown register. */
return 0;
}
static void arm_gen_one_xml_reg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
ARMCPRegInfo *ri, uint32_t ri_key,
int bitsize)
{
g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
g_string_append_printf(s, " group=\"cp_regs\"/>");
dyn_xml->num_cpregs++;
dyn_xml->cpregs_keys[dyn_xml->num_cpregs - 1] = ri_key;
}
static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
gpointer p)
{
uint32_t ri_key = *(uint32_t *)key;
ARMCPRegInfo *ri = value;
RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
GString *s = param->s;
ARMCPU *cpu = ARM_CPU(param->cs);
CPUARMState *env = &cpu->env;
DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_xml;
if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
if (ri->state == ARM_CP_STATE_AA64) {
arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64);
}
} else {
if (ri->state == ARM_CP_STATE_AA32) {
if (!arm_feature(env, ARM_FEATURE_EL3) &&
(ri->secure & ARM_CP_SECSTATE_S)) {
return;
}
if (ri->type & ARM_CP_64BIT) {
arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64);
} else {
arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 32);
}
}
}
}
}
int arm_gen_dynamic_xml(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
GString *s = g_string_new(NULL);
RegisterSysregXmlParam param = {cs, s};
cpu->dyn_xml.num_cpregs = 0;
cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
g_hash_table_size(cpu->cp_regs));
g_string_printf(s, "<?xml version=\"1.0\"?>");
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, &param);
g_string_append_printf(s, "</feature>");
cpu->dyn_xml.desc = g_string_free(s, false);
return cpu->dyn_xml.num_cpregs;
}
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
{
ARMCPU *cpu = ARM_CPU(cs);
if (strcmp(xmlname, "system-registers.xml") == 0) {
return cpu->dyn_xml.desc;
}
return NULL;
}

427
target/arm/helper-sve.h Normal file
View File

@ -0,0 +1,427 @@
/*
* AArch64 SVE specific helper definitions
*
* Copyright (c) 2018 Linaro, Ltd
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
DEF_HELPER_FLAGS_2(sve_predtest1, TCG_CALL_NO_WG, i32, i64, i64)
DEF_HELPER_FLAGS_3(sve_predtest, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_pfirst, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_pnext, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_and_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_and_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_and_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_and_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_eor_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_eor_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_eor_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_eor_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_orr_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_orr_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_orr_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_orr_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_bic_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_bic_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_bic_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_bic_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_add_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_add_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_add_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_add_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sub_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sub_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sub_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sub_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smax_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smax_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smax_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smax_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umax_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umax_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umax_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umax_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smin_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smin_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smin_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smin_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umin_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umin_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umin_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umin_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sabd_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sabd_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sabd_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sabd_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_uabd_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_uabd_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_uabd_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_uabd_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_mul_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_mul_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_mul_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_mul_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smulh_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smulh_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smulh_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_smulh_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umulh_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umulh_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umulh_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_umulh_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_udiv_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_udiv_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzw_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzw_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzw_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_orv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_orv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_orv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_orv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_eorv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_eorv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_eorv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_eorv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_andv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_andv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_andv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_andv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_saddv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_saddv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_saddv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uaddv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uaddv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uaddv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uaddv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_smaxv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_smaxv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_smaxv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_smaxv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_umaxv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_umaxv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_umaxv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_umaxv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_sminv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_sminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_sminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_sminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uminv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_clr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asr_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asr_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asr_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asr_zpzi_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsr_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsr_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsr_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsr_zpzi_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zpzi_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asrd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asrd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asrd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asrd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cls_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cls_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_clz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_clz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_clz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_clz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnt_zpz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnt_zpz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnt_zpz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnt_zpz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnot_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_cnot_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_fabs_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_fabs_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_fabs_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_fneg_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_fneg_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_fneg_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_not_zpz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_not_zpz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_not_zpz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_not_zpz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_sxtb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_sxtb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_sxtb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_uxtb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_uxtb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_uxtb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_sxth_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_sxth_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_uxth_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_uxth_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_sxtw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_uxtw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_abs_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_abs_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_abs_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_abs_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_neg_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_neg_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_neg_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_neg_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mla_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mla_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mla_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mla_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mls_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mls_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mls_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve_mls_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_index_b, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32)
DEF_HELPER_FLAGS_4(sve_index_h, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32)
DEF_HELPER_FLAGS_4(sve_index_s, TCG_CALL_NO_RWG, void, ptr, i32, i32, i32)
DEF_HELPER_FLAGS_4(sve_index_d, TCG_CALL_NO_RWG, void, ptr, i64, i64, i32)
DEF_HELPER_FLAGS_4(sve_asr_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asr_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_asr_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsr_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsr_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsr_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_p32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_p64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_u32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_fexpa_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_fexpa_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_fexpa_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_ftssel_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_ftssel_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_ftssel_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_sqaddi_b, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32)
DEF_HELPER_FLAGS_4(sve_sqaddi_h, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32)
DEF_HELPER_FLAGS_4(sve_sqaddi_s, TCG_CALL_NO_RWG, void, ptr, ptr, s64, i32)
DEF_HELPER_FLAGS_4(sve_sqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, s64, i32)
DEF_HELPER_FLAGS_4(sve_uqaddi_b, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32)
DEF_HELPER_FLAGS_4(sve_uqaddi_h, TCG_CALL_NO_RWG, void, ptr, ptr, s32, i32)
DEF_HELPER_FLAGS_4(sve_uqaddi_s, TCG_CALL_NO_RWG, void, ptr, ptr, s64, i32)
DEF_HELPER_FLAGS_4(sve_uqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_uqsubi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_5(sve_cpy_m_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_5(sve_cpy_m_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_5(sve_cpy_m_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_5(sve_cpy_m_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_cpy_z_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_cpy_z_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_cpy_z_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_ext, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sel_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_orr_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_orn_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_nor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_nand_pppp, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)

57
target/arm/helper.c
View File

@ -215,6 +215,29 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg)
{
ARMCPU *cpu = arm_env_get_cpu(env);
const ARMCPRegInfo *ri;
uint32_t key;
key = cpu->dyn_xml.cpregs_keys[reg];
ri = get_arm_cp_reginfo(cpu->cp_regs, key);
if (ri) {
if (cpreg_field_is_64bit(ri)) {
return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
} else {
return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
}
}
return 0;
}
static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
{
return 0;
}
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
{
/* Return true if the regdef would cause an assertion if you called
@ -690,12 +713,12 @@ static const ARMCPRegInfo cp_reginfo[] = {
* the secure register to be properly reset and migrated. There is also no
* v8 EL1 version of the register so the non-secure instance stands alone.
*/
{ .name = "FCSEIDR(NS)",
{ .name = "FCSEIDR",
.cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
.access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
.fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
{ .name = "FCSEIDR(S)",
{ .name = "FCSEIDR_S",
.cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
.access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
.fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
@ -711,7 +734,7 @@ static const ARMCPRegInfo cp_reginfo[] = {
.access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
{ .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
{ .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
.access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
@ -1981,7 +2004,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
cp15.c14_timer[GTIMER_PHYS].ctl),
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
},
{ .name = "CNTP_CTL(S)",
{ .name = "CNTP_CTL_S",
.cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
.secure = ARM_CP_SECSTATE_S,
.type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
@ -2020,7 +2043,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.accessfn = gt_ptimer_access,
.readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
},
{ .name = "CNTP_TVAL(S)",
{ .name = "CNTP_TVAL_S",
.cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
.secure = ARM_CP_SECSTATE_S,
.type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
@ -2074,7 +2097,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.accessfn = gt_ptimer_access,
.writefn = gt_phys_cval_write, .raw_writefn = raw_write,
},
{ .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
{ .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
.secure = ARM_CP_SECSTATE_S,
.access = PL1_RW | PL0_R,
.type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
@ -5488,6 +5511,9 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0);
}
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
arm_gen_dynamic_xml(cs),
"system-registers.xml", 0);
}
/* Sort alphabetically by type name, except for "any". */
@ -5577,7 +5603,8 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
void *opaque, int state, int secstate,
int crm, int opc1, int opc2)
int crm, int opc1, int opc2,
const char *name)
{
/* Private utility function for define_one_arm_cp_reg_with_opaque():
* add a single reginfo struct to the hash table.
@ -5587,6 +5614,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
r2->name = g_strdup(name);
/* Reset the secure state to the specific incoming state. This is
* necessary as the register may have been defined with both states.
*/
@ -5678,7 +5706,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
if (((r->crm == CP_ANY) && crm != 0) ||
((r->opc1 == CP_ANY) && opc1 != 0) ||
((r->opc2 == CP_ANY) && opc2 != 0)) {
r2->type |= ARM_CP_ALIAS;
r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
}
/* Check that raw accesses are either forbidden or handled. Note that
@ -5818,19 +5846,24 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
/* Under AArch32 CP registers can be common
* (same for secure and non-secure world) or banked.
*/
char *name;
switch (r->secure) {
case ARM_CP_SECSTATE_S:
case ARM_CP_SECSTATE_NS:
add_cpreg_to_hashtable(cpu, r, opaque, state,
r->secure, crm, opc1, opc2);
r->secure, crm, opc1, opc2,
r->name);
break;
default:
name = g_strdup_printf("%s_S", r->name);
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_S,
crm, opc1, opc2);
crm, opc1, opc2, name);
g_free(name);
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2);
crm, opc1, opc2, r->name);
break;
}
} else {
@ -5838,7 +5871,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* of AArch32 */
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2);
crm, opc1, opc2, r->name);
}
}
}

1
target/arm/helper.h
View File

@ -603,4 +603,5 @@ DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG,
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#include "helper-sve.h"
#endif

419
target/arm/sve.decode Normal file
View File

@ -0,0 +1,419 @@
# AArch64 SVE instruction descriptions
#
# Copyright (c) 2017 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
###########################################################################
# Named fields. These are primarily for disjoint fields.
%imm4_16_p1 16:4 !function=plus1
%imm6_22_5 22:1 5:5
%imm8_16_10 16:5 10:3
%imm9_16_10 16:s6 10:3
# A combination of tsz:imm3 -- extract esize.
%tszimm_esz 22:2 5:5 !function=tszimm_esz
# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
%tszimm_shr 22:2 5:5 !function=tszimm_shr
# A combination of tsz:imm3 -- extract (tsz:imm3) - esize
%tszimm_shl 22:2 5:5 !function=tszimm_shl
# Similarly for the tszh/tszl pair at 22/16 for zzi
%tszimm16_esz 22:2 16:5 !function=tszimm_esz
%tszimm16_shr 22:2 16:5 !function=tszimm_shr
%tszimm16_shl 22:2 16:5 !function=tszimm_shl
# Signed 8-bit immediate, optionally shifted left by 8.
%sh8_i8s 5:9 !function=expand_imm_sh8s
# Either a copy of rd (at bit 0), or a different source
# as propagated via the MOVPRFX instruction.
%reg_movprfx 0:5
###########################################################################
# Named attribute sets. These are used to make nice(er) names
# when creating helpers common to those for the individual
# instruction patterns.
&rr_esz rd rn esz
&rri rd rn imm
&rr_dbm rd rn dbm
&rrri rd rn rm imm
&rri_esz rd rn imm esz
&rrr_esz rd rn rm esz
&rpr_esz rd pg rn esz
&rprr_s rd pg rn rm s
&rprr_esz rd pg rn rm esz
&rprrr_esz rd pg rn rm ra esz
&rpri_esz rd pg rn imm esz
&ptrue rd esz pat s
&incdec_cnt rd pat esz imm d u
&incdec2_cnt rd rn pat esz imm d u
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
# Two operand
@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
# Three operand with unused vector element size
@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
# Three predicate operand, with governing predicate, flag setting
@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
# Three operand, vector element size
@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
# Three operand with "memory" size, aka immediate left shift
@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
# Two register operand, with governing predicate, vector element size
@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
&rprr_esz rn=%reg_movprfx
@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
&rprr_esz rm=%reg_movprfx
# Three register operand, with governing predicate, vector element size
@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
&rprrr_esz ra=%reg_movprfx
@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
&rprrr_esz rn=%reg_movprfx
# One register operand, with governing predicate, vector element size
@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
# Two register operands with a 6-bit signed immediate.
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
# Two register operand, one immediate operand, with predicate,
# element size encoded as TSZHL. User must fill in imm.
@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
&rpri_esz rn=%reg_movprfx esz=%tszimm_esz
# Similarly without predicate.
@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
&rri_esz esz=%tszimm16_esz
# Two register operand, one immediate operand, with 4-bit predicate.
# User must fill in imm.
@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
&rpri_esz rn=%reg_movprfx
# Two register operand, one encoded bitmask.
@rdn_dbm ........ .. .... dbm:13 rd:5 \
&rr_dbm rn=%reg_movprfx
# Basic Load/Store with 9-bit immediate offset
@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
&rri imm=%imm9_16_10
@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
&rri imm=%imm9_16_10
# One register, pattern, and uint4+1.
# User must fill in U and D.
@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
&incdec_cnt imm=%imm4_16_p1
@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
&incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
###########################################################################
# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
### SVE Integer Arithmetic - Binary Predicated Group
# SVE bitwise logical vector operations (predicated)
ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
# SVE integer add/subtract vectors (predicated)
ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
# SVE integer min/max/difference (predicated)
SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
# SVE integer multiply/divide (predicated)
MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
# Note that divide requires size >= 2; below 2 is unallocated.
SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
### SVE Integer Reduction Group
# SVE bitwise logical reduction (predicated)
ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
# SVE integer add reduction (predicated)
# Note that saddv requires size != 3.
UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
# SVE integer min/max reduction (predicated)
SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
### SVE Shift by Immediate - Predicated Group
# SVE bitwise shift by immediate (predicated)
ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shr
LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shr
LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shl
ASRD 00000100 .. 000 100 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shr
# SVE bitwise shift by vector (predicated)
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
# SVE bitwise shift by wide elements (predicated)
# Note these require size != 3.
ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
### SVE Integer Arithmetic - Unary Predicated Group
# SVE unary bit operations (predicated)
# Note esz != 0 for FABS and FNEG.
CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
# SVE integer unary operations (predicated)
# Note esz > original size for extensions.
ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
### SVE Integer Multiply-Add Group
# SVE integer multiply-add writing addend (predicated)
MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
# SVE integer multiply-add writing multiplicand (predicated)
MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
### SVE Integer Arithmetic - Unpredicated Group
# SVE integer add/subtract vectors (unpredicated)
ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
### SVE Logical - Unpredicated Group
# SVE bitwise logical operations (unpredicated)
AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
### SVE Index Generation Group
# SVE index generation (immediate start, immediate increment)
INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
# SVE index generation (immediate start, register increment)
INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
# SVE index generation (register start, immediate increment)
INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
# SVE index generation (register start, register increment)
INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
### SVE Stack Allocation Group
# SVE stack frame adjustment
ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
# SVE stack frame size
RDVL 00000100 101 11111 01010 imm:s6 rd:5
### SVE Bitwise Shift - Unpredicated Group
# SVE bitwise shift by immediate (unpredicated)
ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
@rd_rn_tszimm imm=%tszimm16_shr
LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
@rd_rn_tszimm imm=%tszimm16_shr
LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
@rd_rn_tszimm imm=%tszimm16_shl
# SVE bitwise shift by wide elements (unpredicated)
# Note esz != 3
ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
### SVE Compute Vector Address Group
# SVE vector address generation
ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
### SVE Integer Misc - Unpredicated Group
# SVE floating-point exponential accelerator
# Note esz != 0
FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
# SVE floating-point trig select coefficient
# Note esz != 0
FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
### SVE Element Count Group
# SVE element count
CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
# SVE inc/dec register by element count
INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
# SVE saturating inc/dec register by element count
SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
# SVE inc/dec vector by element count
# Note this requires esz != 0.
INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
# SVE saturating inc/dec vector by element count
# Note these require esz != 0.
SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
### SVE Bitwise Immediate Group
# SVE bitwise logical with immediate (unpredicated)
ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
# SVE broadcast bitmask immediate
DUPM 00000101 11 0000 dbm:13 rd:5
### SVE Integer Wide Immediate - Predicated Group
# SVE copy floating-point immediate (predicated)
FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
# SVE copy integer immediate (predicated)
CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
### SVE Permute - Extract Group
# SVE extract vector (immediate offset)
EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
&rrri rn=%reg_movprfx imm=%imm8_16_10
### SVE Predicate Logical Operations Group
# SVE predicate logical operations
AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
### SVE Predicate Misc Group
# SVE predicate test
PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
# SVE predicate initialize
PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
# SVE initialize FFR
SETFFR 00100101 0010 1100 1001 0000 0000 0000
# SVE zero predicate register
PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
# SVE predicate read from FFR (predicated)
RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
# SVE predicate read from FFR (unpredicated)
RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
# SVE FFR write from predicate (WRFFR)
WRFFR 00100101 0010 1000 1001 000 rn:4 00000
# SVE predicate first active
PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
# SVE predicate next active
PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
### SVE Memory - 32-bit Gather and Unsized Contiguous Group
# SVE load predicate register
LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
# SVE load vector register
LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9

1562
target/arm/sve_helper.c Normal file
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File diff suppressed because it is too large Load Diff

119
target/arm/translate-a64.c
View File

@ -36,13 +36,13 @@
#include "exec/log.h"
#include "trace-tcg.h"
#include "translate-a64.h"
static TCGv_i64 cpu_X[32];
static TCGv_i64 cpu_pc;
/* Load/store exclusive handling */
static TCGv_i64 cpu_exclusive_high;
static TCGv_i64 cpu_reg(DisasContext *s, int reg);
static const char *regnames[] = {
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
@ -86,13 +86,6 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp);
/* Note that the gvec expanders operate on offsets + sizes. */
typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
uint32_t, uint32_t);
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
/* initialize TCG globals. */
void a64_translate_init(void)
{
@ -405,22 +398,13 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
}
}
static void unallocated_encoding(DisasContext *s)
void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
#define unsupported_encoding(s, insn) \
do { \
qemu_log_mask(LOG_UNIMP, \
"%s:%d: unsupported instruction encoding 0x%08x " \
"at pc=%016" PRIx64 "\n", \
__FILE__, __LINE__, insn, s->pc - 4); \
unallocated_encoding(s); \
} while (0)
static void init_tmp_a64_array(DisasContext *s)
{
#ifdef CONFIG_DEBUG_TCG
@ -438,13 +422,13 @@ static void free_tmp_a64(DisasContext *s)
init_tmp_a64_array(s);
}
static TCGv_i64 new_tmp_a64(DisasContext *s)
TCGv_i64 new_tmp_a64(DisasContext *s)
{
assert(s->tmp_a64_count < TMP_A64_MAX);
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
}
static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
TCGv_i64 new_tmp_a64_zero(DisasContext *s)
{
TCGv_i64 t = new_tmp_a64(s);
tcg_gen_movi_i64(t, 0);
@ -466,7 +450,7 @@ static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
* to cpu_X[31] and ZR accesses to a temporary which can be discarded.
* This is the point of the _sp forms.
*/
static TCGv_i64 cpu_reg(DisasContext *s, int reg)
TCGv_i64 cpu_reg(DisasContext *s, int reg)
{
if (reg == 31) {
return new_tmp_a64_zero(s);
@ -476,7 +460,7 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg)
}
/* register access for when 31 == SP */
static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
{
return cpu_X[reg];
}
@ -485,7 +469,7 @@ static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
* representing the register contents. This TCGv is an auto-freed
* temporary so it need not be explicitly freed, and may be modified.
*/
static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
{
TCGv_i64 v = new_tmp_a64(s);
if (reg != 31) {
@ -500,7 +484,7 @@ static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
return v;
}
static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
{
TCGv_i64 v = new_tmp_a64(s);
if (sf) {
@ -511,72 +495,6 @@ static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
return v;
}
/* We should have at some point before trying to access an FP register
* done the necessary access check, so assert that
* (a) we did the check and
* (b) we didn't then just plough ahead anyway if it failed.
* Print the instruction pattern in the abort message so we can figure
* out what we need to fix if a user encounters this problem in the wild.
*/
static inline void assert_fp_access_checked(DisasContext *s)
{
#ifdef CONFIG_DEBUG_TCG
if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
fprintf(stderr, "target-arm: FP access check missing for "
"instruction 0x%08x\n", s->insn);
abort();
}
#endif
}
/* Return the offset into CPUARMState of an element of specified
* size, 'element' places in from the least significant end of
* the FP/vector register Qn.
*/
static inline int vec_reg_offset(DisasContext *s, int regno,
int element, TCGMemOp size)
{
int offs = 0;
#ifdef HOST_WORDS_BIGENDIAN
/* This is complicated slightly because vfp.zregs[n].d[0] is
* still the low half and vfp.zregs[n].d[1] the high half
* of the 128 bit vector, even on big endian systems.
* Calculate the offset assuming a fully bigendian 128 bits,
* then XOR to account for the order of the two 64 bit halves.
*/
offs += (16 - ((element + 1) * (1 << size)));
offs ^= 8;
#else
offs += element * (1 << size);
#endif
offs += offsetof(CPUARMState, vfp.zregs[regno]);
assert_fp_access_checked(s);
return offs;
}
/* Return the offset info CPUARMState of the "whole" vector register Qn. */
static inline int vec_full_reg_offset(DisasContext *s, int regno)
{
assert_fp_access_checked(s);
return offsetof(CPUARMState, vfp.zregs[regno]);
}
/* Return a newly allocated pointer to the vector register. */
static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
{
TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
return ret;
}
/* Return the byte size of the "whole" vector register, VL / 8. */
static inline int vec_full_reg_size(DisasContext *s)
{
/* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
In the meantime this is just the AdvSIMD length of 128. */
return 128 / 8;
}
/* Return the offset into CPUARMState of a slice (from
* the least significant end) of FP register Qn (ie
* Dn, Sn, Hn or Bn).
@ -641,7 +559,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
}
}
static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
{
unsigned ofs = fp_reg_offset(s, reg, MO_64);
@ -658,7 +576,7 @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
tcg_temp_free_i64(tmp);
}
static TCGv_ptr get_fpstatus_ptr(bool is_f16)
TCGv_ptr get_fpstatus_ptr(bool is_f16)
{
TCGv_ptr statusptr = tcg_temp_new_ptr();
int offset;
@ -1246,14 +1164,14 @@ static inline bool fp_access_check(DisasContext *s)
/* Check that SVE access is enabled. If it is, return true.
* If not, emit code to generate an appropriate exception and return false.
*/
static inline bool sve_access_check(DisasContext *s)
bool sve_access_check(DisasContext *s)
{
if (s->sve_excp_el) {
gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),
s->sve_excp_el);
return false;
}
return true;
return fp_access_check(s);
}
/*
@ -3419,8 +3337,8 @@ static inline uint64_t bitmask64(unsigned int length)
* value (ie should cause a guest UNDEF exception), and true if they are
* valid, in which case the decoded bit pattern is written to result.
*/
static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
unsigned int imms, unsigned int immr)
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
unsigned int imms, unsigned int immr)
{
uint64_t mask;
unsigned e, levels, s, r;
@ -5650,7 +5568,7 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
* the range 01....1xx to 10....0xx, and the most significant 4 bits of
* the mantissa; see VFPExpandImm() in the v8 ARM ARM.
*/
static uint64_t vfp_expand_imm(int size, uint8_t imm8)
uint64_t vfp_expand_imm(int size, uint8_t imm8)
{
uint64_t imm;
@ -13758,9 +13676,14 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
s->fp_access_checked = false;
switch (extract32(insn, 25, 4)) {
case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
unallocated_encoding(s);
break;
case 0x2:
if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) {
unallocated_encoding(s);
}
break;
case 0x8: case 0x9: /* Data processing - immediate */
disas_data_proc_imm(s, insn);
break;

118
target/arm/translate-a64.h Normal file
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@ -0,0 +1,118 @@
/*
* AArch64 translation, common definitions.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H
void unallocated_encoding(DisasContext *s);
#define unsupported_encoding(s, insn) \
do { \
qemu_log_mask(LOG_UNIMP, \
"%s:%d: unsupported instruction encoding 0x%08x " \
"at pc=%016" PRIx64 "\n", \
__FILE__, __LINE__, insn, s->pc - 4); \
unallocated_encoding(s); \
} while (0)
TCGv_i64 new_tmp_a64(DisasContext *s);
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
TCGv_i64 cpu_reg(DisasContext *s, int reg);
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
TCGv_ptr get_fpstatus_ptr(bool);
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
unsigned int imms, unsigned int immr);
uint64_t vfp_expand_imm(int size, uint8_t imm8);
bool sve_access_check(DisasContext *s);
/* We should have at some point before trying to access an FP register
* done the necessary access check, so assert that
* (a) we did the check and
* (b) we didn't then just plough ahead anyway if it failed.
* Print the instruction pattern in the abort message so we can figure
* out what we need to fix if a user encounters this problem in the wild.
*/
static inline void assert_fp_access_checked(DisasContext *s)
{
#ifdef CONFIG_DEBUG_TCG
if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
fprintf(stderr, "target-arm: FP access check missing for "
"instruction 0x%08x\n", s->insn);
abort();
}
#endif
}
/* Return the offset into CPUARMState of an element of specified
* size, 'element' places in from the least significant end of
* the FP/vector register Qn.
*/
static inline int vec_reg_offset(DisasContext *s, int regno,
int element, TCGMemOp size)
{
int offs = 0;
#ifdef HOST_WORDS_BIGENDIAN
/* This is complicated slightly because vfp.zregs[n].d[0] is
* still the low half and vfp.zregs[n].d[1] the high half
* of the 128 bit vector, even on big endian systems.
* Calculate the offset assuming a fully bigendian 128 bits,
* then XOR to account for the order of the two 64 bit halves.
*/
offs += (16 - ((element + 1) * (1 << size)));
offs ^= 8;
#else
offs += element * (1 << size);
#endif
offs += offsetof(CPUARMState, vfp.zregs[regno]);
assert_fp_access_checked(s);
return offs;
}
/* Return the offset info CPUARMState of the "whole" vector register Qn. */
static inline int vec_full_reg_offset(DisasContext *s, int regno)
{
assert_fp_access_checked(s);
return offsetof(CPUARMState, vfp.zregs[regno]);
}
/* Return a newly allocated pointer to the vector register. */
static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
{
TCGv_ptr ret = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
return ret;
}
/* Return the byte size of the "whole" vector register, VL / 8. */
static inline int vec_full_reg_size(DisasContext *s)
{
return s->sve_len;
}
bool disas_sve(DisasContext *, uint32_t);
/* Note that the gvec expanders operate on offsets + sizes. */
typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
uint32_t, uint32_t);
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
#endif /* TARGET_ARM_TRANSLATE_A64_H */

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