mirror of https://gitee.com/openkylin/qemu.git
target/arm: Implement v8.1M NOCP handling
From v8.1M, disabled-coprocessor handling changes slightly: * coprocessors 8, 9, 14 and 15 are also governed by the cp10 enable bit, like cp11 * an extra range of instruction patterns is considered to be inside the coprocessor space We previously marked these up with TODO comments; implement the correct behaviour. Unfortunately there is no ID register field which indicates this behaviour. We could in theory test an unrelated ID register which indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch >= 3 (low-overhead-loops), but it seems better to simply define a new ARM_FEATURE_V8_1M feature flag and use it for this and other new-in-v8.1M behaviour that isn't identifiable from the ID registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201019151301.2046-3-peter.maydell@linaro.org
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@ -1985,6 +1985,7 @@ enum arm_features {
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ARM_FEATURE_VBAR, /* has cp15 VBAR */
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ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
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ARM_FEATURE_M_MAIN, /* M profile Main Extension */
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ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -29,14 +29,16 @@
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# If the coprocessor is not present or disabled then we will generate
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# the NOCP exception; otherwise we let the insn through to the main decode.
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&nocp cp
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{
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# Special cases which do not take an early NOCP: VLLDM and VLSTM
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VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
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# TODO: VSCCLRM (new in v8.1M) is similar:
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#VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0
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NOCP 111- 1110 ---- ---- ---- cp:4 ---- ----
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NOCP 111- 110- ---- ---- ---- cp:4 ---- ----
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# TODO: From v8.1M onwards we will also want this range to NOCP
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#NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- cp=10
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NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
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NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
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# From v8.1M onwards this range will also NOCP:
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NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- &nocp cp=10
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}
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@ -3459,7 +3459,7 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
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return true;
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}
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static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
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static bool trans_NOCP(DisasContext *s, arg_nocp *a)
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{
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/*
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* Handle M-profile early check for disabled coprocessor:
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@ -3472,7 +3472,11 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
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if (a->cp == 11) {
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a->cp = 10;
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}
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/* TODO: in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
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if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
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(a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
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/* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
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a->cp = 10;
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}
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if (a->cp != 10) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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@ -3489,6 +3493,15 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
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return false;
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}
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static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
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{
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/* This range needs a coprocessor check for v8.1M and later only */
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if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
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return false;
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}
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return trans_NOCP(s, a);
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}
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static bool trans_VINS(DisasContext *s, arg_VINS *a)
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{
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TCGv_i32 rd, rm;
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