mirror of https://gitee.com/openkylin/qemu.git
target/xtensa: rework zero overhead loops implementation
Don't invalidate TB with the end of zero overhead loop when LBEG or LEND change. Instead encode the distance from the start of the page where the TB starts to the LEND in the TB cs_base and generate loopback code when the next PC matches encoded LEND. Distance to a destination within the same page and up to a maximum instruction length into the next page is encoded literally, otherwise it's zero. The distance from LEND to LBEG is also encoded in the cs_base: it's encoded literally when less than 256 or as 0 otherwise. This allows for TB chaining for the loopback branch at the end of a loop for the most common loop sizes. With this change the resulting emulation speed is about 10% higher in softmmu mode on uClibc-ng and LTP tests. Emulation speed in linux user mode is a few percent lower because there's no direct TB chaining between different memory pages. Testing with lower limit on direct TB chaining range shows gradual slowdown to ~15% for the block size of 64 bytes and ~50% for the block size of 32 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Max Filippov
parent
32a1a94dd3
commit
5d630cef4f
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@ -400,6 +400,7 @@ struct XtensaConfig {
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int excm_level;
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int ndepc;
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unsigned inst_fetch_width;
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unsigned max_insn_size;
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uint32_t vecbase;
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uint32_t exception_vector[EXC_MAX];
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unsigned ninterrupt;
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@ -695,6 +696,11 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
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#define XTENSA_TBFLAG_CALLINC_MASK 0x180000
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#define XTENSA_TBFLAG_CALLINC_SHIFT 19
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#define XTENSA_CSBASE_LEND_MASK 0x0000ffff
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#define XTENSA_CSBASE_LEND_SHIFT 0
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#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
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#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
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static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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@ -706,6 +712,32 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
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*flags |= xtensa_get_ring(env);
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if (env->sregs[PS] & PS_EXCM) {
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*flags |= XTENSA_TBFLAG_EXCM;
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} else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
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target_ulong lend_dist =
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env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
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/*
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* 0 in the csbase_lend field means that there may not be a loopback
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* for any instruction that starts inside this page. Any other value
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* means that an instruction that ends at this offset from the page
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* start may loop back and will need loopback code to be generated.
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*
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* lend_dist is 0 when LEND points to the start of the page, but
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* no instruction that starts inside this page may end at offset 0,
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* so it's still correct.
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*
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* When an instruction ends at a page boundary it may only start in
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* the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
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* for the TB that contains this instruction.
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*/
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if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
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target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
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*cs_base = lend_dist;
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if (lbeg_off < 256) {
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*cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
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}
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}
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}
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
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(env->sregs[LITBASE] & 1)) {
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@ -12,8 +12,6 @@ DEF_HELPER_2(rotw, void, env, i32)
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DEF_HELPER_3(window_check, noreturn, env, i32, i32)
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DEF_HELPER_1(restore_owb, void, env)
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DEF_HELPER_2(movsp, void, env, i32)
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DEF_HELPER_2(wsr_lbeg, void, env, i32)
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DEF_HELPER_2(wsr_lend, void, env, i32)
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_1(simcall, void, env)
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#endif
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@ -107,13 +107,6 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
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}
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}
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#else
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static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
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{
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tb_invalidate_phys_addr(vaddr);
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}
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#endif
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void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
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@ -370,23 +363,6 @@ void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
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}
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}
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void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
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{
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if (env->sregs[LBEG] != v) {
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tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
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env->sregs[LBEG] = v;
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}
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}
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void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
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{
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if (env->sregs[LEND] != v) {
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tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
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env->sregs[LEND] = v;
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tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
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}
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}
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void HELPER(dump_state)(CPUXtensaState *env)
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{
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XtensaCPU *cpu = xtensa_env_get_cpu(env);
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@ -457,6 +457,7 @@
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.nareg = XCHAL_NUM_AREGS, \
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.ndepc = (XCHAL_XEA_VERSION >= 2), \
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.inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
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.max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
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EXCEPTIONS_SECTION, \
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INTERRUPTS_SECTION, \
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TLB_SECTION, \
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@ -53,7 +53,7 @@ struct DisasContext {
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uint32_t pc;
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int cring;
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int ring;
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uint32_t lbeg;
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uint32_t lbeg_off;
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uint32_t lend;
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bool sar_5bit;
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@ -390,11 +390,9 @@ static void gen_jump(DisasContext *dc, TCGv dest)
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static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
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{
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TCGv_i32 tmp = tcg_const_i32(dest);
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#ifndef CONFIG_USER_ONLY
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if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
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slot = -1;
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}
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#endif
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gen_jump_slot(dc, tmp, slot);
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tcg_temp_free(tmp);
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}
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@ -420,25 +418,25 @@ static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
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static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
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{
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TCGv_i32 tmp = tcg_const_i32(dest);
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#ifndef CONFIG_USER_ONLY
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if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
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slot = -1;
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}
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#endif
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gen_callw_slot(dc, callinc, tmp, slot);
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tcg_temp_free(tmp);
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}
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static bool gen_check_loop_end(DisasContext *dc, int slot)
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{
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if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
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!(dc->base.tb->flags & XTENSA_TBFLAG_EXCM) &&
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dc->base.pc_next == dc->lend) {
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if (dc->base.pc_next == dc->lend) {
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TCGLabel *label = gen_new_label();
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tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
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tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
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gen_jumpi(dc, dc->lbeg, slot);
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if (dc->lbeg_off) {
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gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot);
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} else {
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gen_jump(dc, cpu_SR[LBEG]);
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}
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gen_set_label(label);
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gen_jumpi(dc, dc->base.pc_next, -1);
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return true;
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@ -534,16 +532,6 @@ static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
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}
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}
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static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
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{
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gen_helper_wsr_lbeg(cpu_env, s);
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}
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static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
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{
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gen_helper_wsr_lend(cpu_env, s);
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}
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static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
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{
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tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
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@ -743,8 +731,6 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
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{
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static void (* const wsr_handler[256])(DisasContext *dc,
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uint32_t sr, TCGv_i32 v) = {
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[LBEG] = gen_wsr_lbeg,
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[LEND] = gen_wsr_lend,
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[SAR] = gen_wsr_sar,
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[BR] = gen_wsr_br,
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[LITBASE] = gen_wsr_litbase,
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@ -906,13 +892,6 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
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}
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dc->base.pc_next = dc->pc + len;
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if (xtensa_option_enabled(dc->config, XTENSA_OPTION_LOOP) &&
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dc->lbeg == dc->pc &&
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((dc->pc ^ (dc->base.pc_next - 1)) & -dc->config->inst_fetch_width)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"unaligned first instruction of a loop (pc = %08x)\n",
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dc->pc);
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}
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for (i = 1; i < len; ++i) {
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b[i] = cpu_ldub_code(env, dc->pc + i);
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}
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@ -1097,8 +1076,10 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
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dc->pc = dc->base.pc_first;
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dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
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dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
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dc->lbeg = env->sregs[LBEG];
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dc->lend = env->sregs[LEND];
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dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >>
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XTENSA_CSBASE_LBEG_OFF_SHIFT;
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dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) +
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(dc->base.pc_first & TARGET_PAGE_MASK);
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dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
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dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
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dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
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@ -1712,12 +1693,10 @@ static void translate_loop(DisasContext *dc, const uint32_t arg[],
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const uint32_t par[])
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{
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uint32_t lend = arg[1];
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TCGv_i32 tmp = tcg_const_i32(lend);
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tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1);
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tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
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gen_helper_wsr_lend(cpu_env, tmp);
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tcg_temp_free(tmp);
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tcg_gen_movi_i32(cpu_SR[LEND], lend);
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if (par[0] != TCG_COND_NEVER) {
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TCGLabel *label = gen_new_label();
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@ -4609,7 +4588,7 @@ static const XtensaOpcodeOps core_ops[] = {
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.translate = translate_wsr,
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.test_ill = test_ill_wsr,
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.par = (const uint32_t[]){LBEG},
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.op_flags = XTENSA_OP_EXIT_TB_0,
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.op_flags = XTENSA_OP_EXIT_TB_M1,
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.windowed_register_op = 0x1,
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}, {
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.name = "wsr.lcount",
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@ -4622,7 +4601,7 @@ static const XtensaOpcodeOps core_ops[] = {
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.translate = translate_wsr,
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.test_ill = test_ill_wsr,
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.par = (const uint32_t[]){LEND},
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.op_flags = XTENSA_OP_EXIT_TB_0,
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.op_flags = XTENSA_OP_EXIT_TB_M1,
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.windowed_register_op = 0x1,
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}, {
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.name = "wsr.litbase",
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@ -5183,7 +5162,7 @@ static const XtensaOpcodeOps core_ops[] = {
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.translate = translate_xsr,
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.test_ill = test_ill_xsr,
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.par = (const uint32_t[]){LBEG},
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.op_flags = XTENSA_OP_EXIT_TB_0,
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.op_flags = XTENSA_OP_EXIT_TB_M1,
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.windowed_register_op = 0x1,
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}, {
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.name = "xsr.lcount",
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@ -5196,7 +5175,7 @@ static const XtensaOpcodeOps core_ops[] = {
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.translate = translate_xsr,
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.test_ill = test_ill_xsr,
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.par = (const uint32_t[]){LEND},
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.op_flags = XTENSA_OP_EXIT_TB_0,
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.op_flags = XTENSA_OP_EXIT_TB_M1,
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.windowed_register_op = 0x1,
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}, {
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.name = "xsr.litbase",
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