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ppc patch queue 2017-11-08 

Here's the current set of accumulated ppc patches for qemu-2.11.
 Since we're now in hard freeze these are all bugfixes (although some
 fix a bug by way of a cleanup).
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20171108' into staging

ppc patch queue 2017-11-08

Here's the current set of accumulated ppc patches for qemu-2.11.
Since we're now in hard freeze these are all bugfixes (although some
fix a bug by way of a cleanup).

# gpg: Signature made Wed 08 Nov 2017 08:10:38 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.11-20171108:
  e500: ppce500_init_mpic() return device instead of IRQ array
  hw/display/sm501: Fix comment in sm501_sysbus_class_init()
  ppc: fix setting of compat mode

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-11-10 15:05:56 +00:00
parent b0fbe46ad8 c91c187f71
commit 6058bfb00a
3 changed files with 15 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/display/sm501.c
View File

@ -1758,7 +1758,7 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
dc->reset = sm501_reset_sysbus;
dc->vmsd = &vmstate_sm501_sysbus;
/* Note: pointer property "chr-state" may remain null, thus
* no need for dc->cannot_instantiate_with_device_add_yet = true;
* no need for dc->user_creatable = false;
*/
}

32
hw/ppc/e500.c
View File

@ -729,15 +729,13 @@ static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
return dev;
}
static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params,
MemoryRegion *ccsr, qemu_irq **irqs)
static DeviceState *ppce500_init_mpic(MachineState *machine,
PPCE500Params *params,
MemoryRegion *ccsr,
qemu_irq **irqs)
{
qemu_irq *mpic;
DeviceState *dev = NULL;
SysBusDevice *s;
int i;
mpic = g_new0(qemu_irq, 256);
if (kvm_enabled()) {
Error *err = NULL;
@ -756,15 +754,11 @@ static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params,
dev = ppce500_init_mpic_qemu(params, irqs);
}
for (i = 0; i < 256; i++) {
mpic[i] = qdev_get_gpio_in(dev, i);
}
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
s->mmio[0].memory);
return mpic;
return dev;
}
static void ppce500_power_off(void *opaque, int line, int on)
@ -796,8 +790,8 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
/* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
* 4 respectively */
unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
qemu_irq **irqs, *mpic;
DeviceState *dev;
qemu_irq **irqs;
DeviceState *dev, *mpicdev;
CPUPPCState *firstenv = NULL;
MemoryRegion *ccsr_addr_space;
SysBusDevice *s;
@ -866,18 +860,18 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
ccsr_addr_space);
mpic = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
/* Serial */
if (serial_hds[0]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
0, mpic[42], 399193,
0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hds[0], DEVICE_BIG_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
0, mpic[42], 399193,
0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hds[1], DEVICE_BIG_ENDIAN);
}
@ -895,7 +889,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]);
sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
}
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
@ -926,7 +920,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
dev = qdev_create(NULL, "mpc8xxx_gpio");
s = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]);
sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
sysbus_mmio_get_region(s, 0));
@ -946,7 +940,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
for (i = 0; i < params->platform_bus_num_irqs; i++) {
int irqn = params->platform_bus_first_irq + i;
sysbus_connect_irq(s, i, mpic[irqn]);
sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
}
memory_region_add_subregion(address_space_mem,

2
target/ppc/compat.c
View File

@ -141,7 +141,7 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
cpu_synchronize_state(CPU(cpu));
if (kvm_enabled() && cpu->compat_pvr != compat_pvr) {
int ret = kvmppc_set_compat(cpu, cpu->compat_pvr);
int ret = kvmppc_set_compat(cpu, compat_pvr);
if (ret < 0) {
error_setg_errno(errp, -ret,
"Unable to set CPU compatibility mode in KVM");