mirror of https://gitee.com/openkylin/qemu.git
pc: acpi-build: create PCI0._CRS dynamically
Replace template patching and runtime calculation in _CRS() method with static _CRS defined in SSDT. No functional change except of as mentined above and _CRS being moved from DSDT to SSDT. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Igor Mammedov
Michael S. Tsirkin
parent
9dd5c40ddf
commit
60efd4297d
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@ -346,24 +346,6 @@ static void acpi_align_size(GArray *blob, unsigned align)
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g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
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}
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/* Set a value within table in a safe manner */
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#define ACPI_BUILD_SET_LE(table, size, off, bits, val) \
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do { \
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uint64_t ACPI_BUILD_SET_LE_val = cpu_to_le64(val); \
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memcpy(acpi_data_get_ptr(table, size, off, \
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(bits) / BITS_PER_BYTE), \
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&ACPI_BUILD_SET_LE_val, \
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(bits) / BITS_PER_BYTE); \
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} while (0)
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static inline void *acpi_data_get_ptr(uint8_t *table_data, unsigned table_size,
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unsigned off, unsigned size)
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{
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assert(off + size > off);
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assert(off + size <= table_size);
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return table_data + off;
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}
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static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
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{
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uint32_t offset = cpu_to_le32(table_data->len);
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@ -860,22 +842,6 @@ static void build_pci_bus_end(PCIBus *bus, void *bus_state)
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g_free(child);
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}
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static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
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{
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ACPI_BUILD_SET_LE(start, size, acpi_pci32_start[0], 32, pci->w32.begin);
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ACPI_BUILD_SET_LE(start, size, acpi_pci32_end[0], 32, pci->w32.end - 1);
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if (pci->w64.end || pci->w64.begin) {
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ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 1);
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ACPI_BUILD_SET_LE(start, size, acpi_pci64_start[0], 64, pci->w64.begin);
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ACPI_BUILD_SET_LE(start, size, acpi_pci64_end[0], 64, pci->w64.end - 1);
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ACPI_BUILD_SET_LE(start, size, acpi_pci64_length[0], 64, pci->w64.end - pci->w64.begin);
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} else {
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ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 0);
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}
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}
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static void
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build_ssdt(GArray *table_data, GArray *linker,
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AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
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@ -898,9 +864,59 @@ build_ssdt(GArray *table_data, GArray *linker,
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ssdt_ptr = acpi_data_push(ssdt->buf, sizeof(ssdp_misc_aml));
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memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
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patch_pci_windows(pci, ssdt_ptr, sizeof(ssdp_misc_aml));
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scope = aml_scope("\\_SB.PCI0");
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/* build PCI0._CRS */
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crs = aml_resource_template();
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aml_append(crs,
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aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
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0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
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aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
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if (ich9_lpc_find()) { /* Q35 */
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
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} else { /* piix4 */
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0x0000, 0x0D00, 0xADFF, 0x0000, 0xA100));
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0x0000, 0xAE0F, 0xAEFF, 0x0000, 0x00F1));
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0x0000, 0xAF20, 0xAFDF, 0x0000, 0x00C0));
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aml_append(crs,
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aml_word_io(aml_min_fixed, aml_max_fixed,
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aml_pos_decode, aml_entire_range,
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0x0000, 0xAFE4, 0xFFFF, 0x0000, 0x501C));
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}
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aml_append(crs,
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aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
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aml_cacheable, aml_ReadWrite,
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0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
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aml_append(crs,
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aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
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aml_non_cacheable, aml_ReadWrite,
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0, pci->w32.begin, pci->w32.end - 1, 0,
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pci->w32.end - pci->w32.begin));
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if (pci->w64.begin) {
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aml_append(crs,
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aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
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aml_cacheable, aml_ReadWrite,
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0, pci->w64.begin, pci->w64.end - 1, 0,
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pci->w64.end - pci->w64.begin));
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}
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aml_append(scope, aml_name_decl("_CRS", crs));
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/* reserve PCIHP resources */
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if (pm->pcihp_io_len) {
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dev = aml_device("PHPR");
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@ -1,92 +0,0 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* PCI CRS (current resources) definition. */
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Scope(\_SB.PCI0) {
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Name(CRES, ResourceTemplate() {
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WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x00FF, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0100, // Address Length
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,, )
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IO(Decode16,
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0x0CF8, // Address Range Minimum
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0x0CF8, // Address Range Maximum
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0x01, // Address Alignment
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0x08, // Address Length
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)
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BOARD_SPECIFIC_PCI_RESOURSES
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, // Address Space Granularity
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0x000A0000, // Address Range Minimum
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0x000BFFFF, // Address Range Maximum
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0x00000000, // Address Translation Offset
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0x00020000, // Address Length
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,, , AddressRangeMemory, TypeStatic)
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, // Address Space Granularity
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0xE0000000, // Address Range Minimum
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0xFEBFFFFF, // Address Range Maximum
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0x00000000, // Address Translation Offset
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0x1EC00000, // Address Length
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,, PW32, AddressRangeMemory, TypeStatic)
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})
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Name(CR64, ResourceTemplate() {
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QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, // Address Space Granularity
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0x8000000000, // Address Range Minimum
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0xFFFFFFFFFF, // Address Range Maximum
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0x00000000, // Address Translation Offset
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0x8000000000, // Address Length
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,, PW64, AddressRangeMemory, TypeStatic)
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})
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Method(_CRS, 0) {
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/* Fields provided by dynamically created ssdt */
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External(P0S, IntObj)
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External(P0E, IntObj)
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External(P1V, IntObj)
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External(P1S, BuffObj)
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External(P1E, BuffObj)
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External(P1L, BuffObj)
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/* fixup 32bit pci io window */
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CreateDWordField(CRES, \_SB.PCI0.PW32._MIN, PS32)
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CreateDWordField(CRES, \_SB.PCI0.PW32._MAX, PE32)
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CreateDWordField(CRES, \_SB.PCI0.PW32._LEN, PL32)
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Store(P0S, PS32)
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Store(P0E, PE32)
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Store(Add(Subtract(P0E, P0S), 1), PL32)
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If (LEqual(P1V, Zero)) {
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Return (CRES)
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}
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/* fixup 64bit pci io window */
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CreateQWordField(CR64, \_SB.PCI0.PW64._MIN, PS64)
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CreateQWordField(CR64, \_SB.PCI0.PW64._MAX, PE64)
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CreateQWordField(CR64, \_SB.PCI0.PW64._LEN, PL64)
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Store(P1S, PS64)
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Store(P1E, PE64)
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Store(P1L, PL64)
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/* add window and return result */
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ConcatenateResTemplate(CRES, CR64, Local0)
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Return (Local0)
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}
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}
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@ -31,50 +31,6 @@ DefinitionBlock (
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#include "acpi-dsdt-dbug.dsl"
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/****************************************************************
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* PCI Bus definition
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****************************************************************/
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#define BOARD_SPECIFIC_PCI_RESOURSES \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0x0000, \
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0x0CF7, \
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0x0000, \
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0x0CF8, \
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,, , TypeStatic) \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0x0D00, \
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0xADFF, \
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0x0000, \
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0xA100, \
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,, , TypeStatic) \
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/* 0xae00-0xae0e hole for PCI hotplug, hw/acpi/piix4.c:PCI_HOTPLUG_ADDR */ \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0xAE0F, \
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0xAEFF, \
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0x0000, \
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0x00F1, \
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,, , TypeStatic) \
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/* 0xaf00-0xaf1f hole for CPU hotplug, hw/acpi/piix4.c:PIIX4_PROC_BASE */ \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0xAF20, \
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0xAFDF, \
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0x0000, \
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0x00C0, \
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,, , TypeStatic) \
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/* 0xafe0-0xafe3 hole for ACPI.GPE0, hw/acpi/piix4.c:GPE_BASE */ \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0xAFE4, \
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0xFFFF, \
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0x0000, \
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0x501C, \
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,, , TypeStatic)
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Scope(\_SB) {
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Device(PCI0) {
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Name(_HID, EisaId("PNP0A03"))
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@ -85,7 +41,6 @@ DefinitionBlock (
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}
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}
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#include "acpi-dsdt-pci-crs.dsl"
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#include "acpi-dsdt-hpet.dsl"
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@ -48,23 +48,6 @@ DefinitionBlock (
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/****************************************************************
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* PCI Bus definition
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****************************************************************/
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#define BOARD_SPECIFIC_PCI_RESOURSES \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0x0000, \
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0x0CD7, \
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0x0000, \
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0x0CD8, \
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,, , TypeStatic) \
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/* 0xcd8-0xcf7 hole for CPU hotplug, hw/acpi/ich9.c:ICH9_PROC_BASE */ \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0x0D00, \
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0xFFFF, \
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0x0000, \
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0xF300, \
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,, , TypeStatic)
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Scope(\_SB) {
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Device(PCI0) {
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Name(_HID, EisaId("PNP0A08"))
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@ -131,7 +114,6 @@ DefinitionBlock (
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}
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}
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#include "acpi-dsdt-pci-crs.dsl"
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#include "acpi-dsdt-hpet.dsl"
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@ -18,23 +18,4 @@ ACPI_EXTRACT_ALL_CODE ssdp_misc_aml
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DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1)
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{
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/****************************************************************
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* PCI memory ranges
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****************************************************************/
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Scope(\) {
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ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_start
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Name(P0S, 0x12345678)
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ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_end
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Name(P0E, 0x12345678)
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ACPI_EXTRACT_NAME_BYTE_CONST acpi_pci64_valid
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Name(P1V, 0x12)
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ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_start
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Name(P1S, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
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ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_end
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Name(P1E, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
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ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_length
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Name(P1L, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
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}
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}
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