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hw/i386: Build-time assertion on pc/q35 reset register being identical. 

This adds a clarifying comment and build time assert to the FADT reset register field initialisation: the reset register is the same on both machine types.

Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu>
Message-Id: <1489558827-28971-3-git-send-email-phil@philjordan.eu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Phil Dennis-Jordan 2017-03-15 19:20:27 +13:00 committed by Paolo Bonzini
parent 77af8a2b95
commit 6103451aeb
3 changed files with 9 additions and 6 deletions
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3
hw/i386/acpi-build.c
View File

@ -310,6 +310,9 @@ static void fadt_setup(AcpiFadtDescriptorRev3 *fadt, AcpiPmInfo *pm)
fadt->reset_register.space_id = AML_SYSTEM_IO; fadt->reset_register.space_id = AML_SYSTEM_IO;
fadt->reset_register.bit_width = 8; fadt->reset_register.bit_width = 8;
fadt->reset_register.address = cpu_to_le64(ICH9_RST_CNT_IOPORT); fadt->reset_register.address = cpu_to_le64(ICH9_RST_CNT_IOPORT);
/* The above need not be conditional on machine type because the reset port
* happens to be the same on PIIX (pc) and ICH9 (q35). */
QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
fadt->xpm1a_event_block.space_id = AML_SYSTEM_IO; fadt->xpm1a_event_block.space_id = AML_SYSTEM_IO;
fadt->xpm1a_event_block.bit_width = fadt->pm1_evt_len * 8; fadt->xpm1a_event_block.bit_width = fadt->pm1_evt_len * 8;

6
hw/pci-host/piix.c
View File

@ -58,12 +58,6 @@ typedef struct I440FXState {
#define XEN_PIIX_NUM_PIRQS 128ULL #define XEN_PIIX_NUM_PIRQS 128ULL
#define PIIX_PIRQC 0x60 #define PIIX_PIRQC 0x60
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
*/
#define RCR_IOPORT 0xcf9
typedef struct PIIX3State { typedef struct PIIX3State {
PCIDevice dev; PCIDevice dev;

6
include/hw/i386/pc.h
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@ -303,6 +303,12 @@ typedef struct PCII440FXState PCII440FXState;
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
*/
#define RCR_IOPORT 0xcf9
PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state, int *piix_devfn, PCII440FXState **pi440fx_state, int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic, ISABus **isa_bus, qemu_irq *pic,