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hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf() 

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-6-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2019-06-25 00:28:39 +02:00 committed by Aleksandar Markovic
parent b61104b228
commit 641ca2bfcd
1 changed files with 37 additions and 11 deletions
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48
hw/mips/gt64xxx_pci.c
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@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/mips/mips.h" #include "hw/mips/mips.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
@ -466,12 +467,20 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_CPUERR_DATAHI: case GT_CPUERR_DATAHI:
case GT_CPUERR_PARITY: case GT_CPUERR_PARITY:
/* Read-only registers, do nothing */ /* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
/* CPU Sync Barrier */ /* CPU Sync Barrier */
case GT_PCI0SYNC: case GT_PCI0SYNC:
case GT_PCI1SYNC: case GT_PCI1SYNC:
/* Read-only registers, do nothing */ /* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
/* SDRAM and Device Address Decode */ /* SDRAM and Device Address Decode */
@ -510,7 +519,10 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_DEV_B3: case GT_DEV_B3:
case GT_DEV_BOOT: case GT_DEV_BOOT:
/* Not implemented */ /* Not implemented */
DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2); qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented device register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
/* ECC */ /* ECC */
@ -520,6 +532,10 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_ECC_CALC: case GT_ECC_CALC:
case GT_ECC_ERRADDR: case GT_ECC_ERRADDR:
/* Read-only registers, do nothing */ /* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
/* DMA Record */ /* DMA Record */
@ -543,23 +559,20 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_DMA1_CUR: case GT_DMA1_CUR:
case GT_DMA2_CUR: case GT_DMA2_CUR:
case GT_DMA3_CUR: case GT_DMA3_CUR:
/* Not implemented */
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* DMA Channel Control */ /* DMA Channel Control */
case GT_DMA0_CTRL: case GT_DMA0_CTRL:
case GT_DMA1_CTRL: case GT_DMA1_CTRL:
case GT_DMA2_CTRL: case GT_DMA2_CTRL:
case GT_DMA3_CTRL: case GT_DMA3_CTRL:
/* Not implemented */
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* DMA Arbiter */ /* DMA Arbiter */
case GT_DMA_ARB: case GT_DMA_ARB:
/* Not implemented */ /* Not implemented */
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented DMA register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
/* Timer/Counter */ /* Timer/Counter */
@ -569,7 +582,10 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_TC3: case GT_TC3:
case GT_TC_CONTROL: case GT_TC_CONTROL:
/* Not implemented */ /* Not implemented */
DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2); qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented timer register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
/* PCI Internal */ /* PCI Internal */
@ -610,6 +626,10 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_PCI1_CFGADDR: case GT_PCI1_CFGADDR:
case GT_PCI1_CFGDATA: case GT_PCI1_CFGDATA:
/* not implemented */ /* not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented timer register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
case GT_PCI0_CFGADDR: case GT_PCI0_CFGADDR:
phb->config_reg = val & 0x80fffffc; phb->config_reg = val & 0x80fffffc;
@ -666,7 +686,10 @@ static void gt64120_writel(void *opaque, hwaddr addr,
break; break;
default: default:
DPRINTF ("Bad register offset 0x%x\n", (int)addr); qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break; break;
} }
} }
@ -940,7 +963,10 @@ static uint64_t gt64120_readl(void *opaque,
default: default:
val = s->regs[saddr]; val = s->regs[saddr];
DPRINTF ("Bad register offset 0x%x\n", (int)addr); qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register read "
"reg:0x03%x size:%u value:0x%0*x\n",
saddr << 2, size, size << 1, val);
break; break;
} }