mirror of https://gitee.com/openkylin/qemu.git
hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv
Rather than having the virt machine model create an a15mpcore_priv device regardless of the actual CPU type in order to instantiate the GIC, move to having the machine model create the GIC directly. This corresponds to a system which uses a standalone GIC (eg the GIC-400) rather than the one built in to the CPU core. The primary motivation for this is to support the Cortex-A57, which for a KVM configuration will use a GICv2, which is not built into the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-2-git-send-email-peter.maydell@linaro.org
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@ -75,8 +75,6 @@ typedef struct MemMapEntry {
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typedef struct VirtBoardInfo {
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struct arm_boot_info bootinfo;
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const char *cpu_model;
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const char *qdevname;
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const char *gic_compatible;
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const MemMapEntry *memmap;
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const int *irqmap;
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int smp_cpus;
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@ -117,16 +115,11 @@ static const int a15irqmap[] = {
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static VirtBoardInfo machines[] = {
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{
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.cpu_model = "cortex-a15",
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.qdevname = "a15mpcore_priv",
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.gic_compatible = "arm,cortex-a15-gic",
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.memmap = a15memmap,
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.irqmap = a15irqmap,
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},
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{
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.cpu_model = "host",
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/* We use the A15 private peripheral model to get a V2 GIC */
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.qdevname = "a15mpcore_priv",
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.gic_compatible = "arm,cortex-a15-gic",
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.memmap = a15memmap,
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.irqmap = a15irqmap,
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},
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@ -251,8 +244,9 @@ static void fdt_add_gic_node(const VirtBoardInfo *vbi)
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qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle);
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qemu_fdt_add_subnode(vbi->fdt, "/intc");
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/* 'cortex-a15-gic' means 'GIC v2' */
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qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
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vbi->gic_compatible);
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"arm,cortex-a15-gic");
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3);
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qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
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@ -263,6 +257,56 @@ static void fdt_add_gic_node(const VirtBoardInfo *vbi)
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle);
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}
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static void create_gic(const VirtBoardInfo *vbi, qemu_irq *pic)
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{
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/* We create a standalone GIC v2 */
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DeviceState *gicdev;
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SysBusDevice *gicbusdev;
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const char *gictype = "arm_gic";
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int i;
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if (kvm_irqchip_in_kernel()) {
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gictype = "kvm-arm-gic";
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}
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gicdev = qdev_create(NULL, gictype);
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qdev_prop_set_uint32(gicdev, "revision", 2);
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qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
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/* Note that the num-irq property counts both internal and external
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* interrupts; there are always 32 of the former (mandated by GIC spec).
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*/
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qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
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qdev_init_nofail(gicdev);
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gicbusdev = SYS_BUS_DEVICE(gicdev);
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sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base);
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sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
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/* Wire the outputs from each CPU's generic timer to the
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* appropriate GIC PPI inputs, and the GIC's IRQ output to
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* the CPU's IRQ input.
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*/
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for (i = 0; i < smp_cpus; i++) {
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DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
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int ppibase = NUM_IRQS + i * 32;
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/* physical timer; we wire it up to the non-secure timer's ID,
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* since a real A15 always has TrustZone but QEMU doesn't.
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*/
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qdev_connect_gpio_out(cpudev, 0,
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qdev_get_gpio_in(gicdev, ppibase + 30));
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/* virtual timer */
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qdev_connect_gpio_out(cpudev, 1,
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qdev_get_gpio_in(gicdev, ppibase + 27));
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sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
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}
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for (i = 0; i < NUM_IRQS; i++) {
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pic[i] = qdev_get_gpio_in(gicdev, i);
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}
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fdt_add_gic_node(vbi);
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}
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static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic)
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{
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char *nodename;
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@ -340,8 +384,6 @@ static void machvirt_init(QEMUMachineInitArgs *args)
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MemoryRegion *sysmem = get_system_memory();
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int n;
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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DeviceState *dev;
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SysBusDevice *busdev;
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const char *cpu_model = args->cpu_model;
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VirtBoardInfo *vbi;
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@ -404,25 +446,7 @@ static void machvirt_init(QEMUMachineInitArgs *args)
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vmstate_register_ram_global(ram);
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memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram);
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dev = qdev_create(NULL, vbi->qdevname);
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qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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/* Note that the num-irq property counts both internal and external
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* interrupts; there are always 32 of the former (mandated by GIC spec).
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*/
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qdev_prop_set_uint32(dev, "num-irq", NUM_IRQS + 32);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, vbi->memmap[VIRT_CPUPERIPHS].base);
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fdt_add_gic_node(vbi);
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for (n = 0; n < smp_cpus; n++) {
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DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
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sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
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}
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for (n = 0; n < NUM_IRQS; n++) {
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pic[n] = qdev_get_gpio_in(dev, n);
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}
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create_gic(vbi, pic);
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create_uart(vbi, pic);
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