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target-arm: Move TB flags down to fill gap 

Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the
bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and
ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Peter Maydell 2015-05-29 11:28:53 +01:00
parent 9dbbc748d6
commit 647f767ba3
1 changed files with 2 additions and 2 deletions
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4
target-arm/cpu.h
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@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState *env)
/* We store the bottom two bits of the CPAR as TB flags and handle /* We store the bottom two bits of the CPAR as TB flags and handle
* checks on the other bits at runtime * checks on the other bits at runtime
*/ */
#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
/* Indicates whether cp register reads and writes by guest code should access /* Indicates whether cp register reads and writes by guest code should access
* the secure or nonsecure bank of banked registers; note that this is not * the secure or nonsecure bank of banked registers; note that this is not
* the same thing as the current security state of the processor! * the same thing as the current security state of the processor!
*/ */
#define ARM_TBFLAG_NS_SHIFT 22 #define ARM_TBFLAG_NS_SHIFT 19
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
/* Bit usage when in AArch64 state: currently we have no A64 specific bits */ /* Bit usage when in AArch64 state: currently we have no A64 specific bits */