mirror of https://gitee.com/openkylin/qemu.git
target-arm: Move CTR setup to per cpu init fns
Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Peter Maydell
parent
bd35c3553b
commit
64e1671fd4
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@ -73,6 +73,7 @@ typedef struct ARMCPU {
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uint32_t reset_fpsid;
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uint32_t mvfr0;
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uint32_t mvfr1;
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uint32_t ctr;
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} ARMCPU;
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static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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@ -101,6 +101,7 @@ static void arm926_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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cpu->midr = ARM_CPUID_ARM926;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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}
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static void arm946_initfn(Object *obj)
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@ -109,6 +110,7 @@ static void arm946_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_MPU);
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cpu->midr = ARM_CPUID_ARM946;
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cpu->ctr = 0x0f004006;
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}
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static void arm1026_initfn(Object *obj)
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@ -119,6 +121,7 @@ static void arm1026_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_AUXCR);
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cpu->midr = ARM_CPUID_ARM1026;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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}
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static void arm1136_r2_initfn(Object *obj)
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@ -130,6 +133,7 @@ static void arm1136_r2_initfn(Object *obj)
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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}
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static void arm1136_initfn(Object *obj)
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@ -142,6 +146,7 @@ static void arm1136_initfn(Object *obj)
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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}
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static void arm1176_initfn(Object *obj)
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@ -154,6 +159,7 @@ static void arm1176_initfn(Object *obj)
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cpu->reset_fpsid = 0x410120b5;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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}
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static void arm11mpcore_initfn(Object *obj)
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@ -166,6 +172,7 @@ static void arm11mpcore_initfn(Object *obj)
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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}
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static void cortex_m3_initfn(Object *obj)
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@ -187,6 +194,7 @@ static void cortex_a8_initfn(Object *obj)
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cpu->reset_fpsid = 0x410330c0;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x00011100;
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cpu->ctr = 0x82048004;
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}
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static void cortex_a9_initfn(Object *obj)
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@ -206,6 +214,7 @@ static void cortex_a9_initfn(Object *obj)
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cpu->reset_fpsid = 0x41033090;
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cpu->mvfr0 = 0x11110222;
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cpu->mvfr1 = 0x01111111;
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cpu->ctr = 0x80038003;
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}
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static void cortex_a15_initfn(Object *obj)
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@ -223,6 +232,7 @@ static void cortex_a15_initfn(Object *obj)
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cpu->reset_fpsid = 0x410430f0;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x11111111;
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cpu->ctr = 0x8444c004;
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}
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static void ti925t_initfn(Object *obj)
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@ -231,6 +241,7 @@ static void ti925t_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V4T);
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set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
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cpu->midr = ARM_CPUID_TI925T;
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cpu->ctr = 0x5109149;
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}
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static void sa1100_initfn(Object *obj)
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@ -253,6 +264,7 @@ static void pxa250_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA250;
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cpu->ctr = 0xd172172;
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}
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static void pxa255_initfn(Object *obj)
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@ -261,6 +273,7 @@ static void pxa255_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA255;
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cpu->ctr = 0xd172172;
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}
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static void pxa260_initfn(Object *obj)
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@ -269,6 +282,7 @@ static void pxa260_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA260;
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cpu->ctr = 0xd172172;
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}
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static void pxa261_initfn(Object *obj)
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@ -277,6 +291,7 @@ static void pxa261_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA261;
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cpu->ctr = 0xd172172;
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}
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static void pxa262_initfn(Object *obj)
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@ -285,6 +300,7 @@ static void pxa262_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA262;
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cpu->ctr = 0xd172172;
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}
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static void pxa270a0_initfn(Object *obj)
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@ -294,6 +310,7 @@ static void pxa270a0_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_A0;
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cpu->ctr = 0xd172172;
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}
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static void pxa270a1_initfn(Object *obj)
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@ -303,6 +320,7 @@ static void pxa270a1_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_A1;
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cpu->ctr = 0xd172172;
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}
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static void pxa270b0_initfn(Object *obj)
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@ -312,6 +330,7 @@ static void pxa270b0_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_B0;
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cpu->ctr = 0xd172172;
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}
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static void pxa270b1_initfn(Object *obj)
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@ -321,6 +340,7 @@ static void pxa270b1_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_B1;
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cpu->ctr = 0xd172172;
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}
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static void pxa270c0_initfn(Object *obj)
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@ -330,6 +350,7 @@ static void pxa270c0_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_C0;
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cpu->ctr = 0xd172172;
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}
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static void pxa270c5_initfn(Object *obj)
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@ -339,6 +360,7 @@ static void pxa270c5_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_C5;
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cpu->ctr = 0xd172172;
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}
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static void arm_any_initfn(Object *obj)
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@ -50,15 +50,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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{
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switch (id) {
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case ARM_CPUID_ARM926:
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_ARM946:
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env->cp15.c0_cachetype = 0x0f004006;
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env->cp15.c1_sys = 0x00000078;
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break;
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case ARM_CPUID_ARM1026:
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_ARM1136:
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@ -74,24 +71,20 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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*/
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memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM1176:
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memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM11MPCORE:
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memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x1dd20d2;
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break;
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case ARM_CPUID_CORTEXA8:
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memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x82048004;
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env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
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env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
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env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
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@ -101,7 +94,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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case ARM_CPUID_CORTEXA9:
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memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x80038003;
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env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
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env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
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env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
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@ -110,7 +102,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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case ARM_CPUID_CORTEXA15:
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memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x8444c004;
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env->cp15.c0_clid = 0x0a200023;
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env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
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env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
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@ -123,7 +114,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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break;
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case ARM_CPUID_TI915T:
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case ARM_CPUID_TI925T:
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env->cp15.c0_cachetype = 0x5109149;
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env->cp15.c1_sys = 0x00000070;
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env->cp15.c15_i_max = 0x000;
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env->cp15.c15_i_min = 0xff0;
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@ -134,7 +124,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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case ARM_CPUID_PXA261:
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case ARM_CPUID_PXA262:
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/* JTAG_ID is ((id << 28) | 0x09265013) */
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env->cp15.c0_cachetype = 0xd172172;
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env->cp15.c1_sys = 0x00000078;
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break;
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case ARM_CPUID_PXA270_A0:
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@ -145,7 +134,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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case ARM_CPUID_PXA270_C5:
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/* JTAG_ID is ((id << 28) | 0x09265013) */
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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env->cp15.c0_cachetype = 0xd172172;
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env->cp15.c1_sys = 0x00000078;
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break;
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case ARM_CPUID_SA1100:
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@ -184,6 +172,7 @@ void cpu_state_reset(CPUARMState *env)
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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env->cp15.c0_cachetype = cpu->ctr;
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#if defined (CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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