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Fix dp8393x when used in big-endian/double-word mode 

(fix DHCP address allocation for q800 machine)
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Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging

Fix dp8393x when used in big-endian/double-word mode
(fix DHCP address allocation for q800 machine)

# gpg: Signature made Fri 08 Nov 2019 20:38:21 GMT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/q800-branch-pull-request:
  dp8393x: fix dp8393x_receive()
  dp8393x: put the DMA buffer in the state structure

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-11-11 09:23:46 +00:00
parent 1cee80fa66 c744cf7879
commit 654efcb511
1 changed files with 57 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
hw/net/dp8393x.c
View File

@ -171,6 +171,7 @@ typedef struct dp8393xState {
/* Temporaries */
uint8_t tx_buffer[0x10000];
uint16_t data[12];
int loopback_packet;
/* Memory access */
@ -224,26 +225,25 @@ static uint32_t dp8393x_wt(dp8393xState *s)
return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
}
static uint16_t dp8393x_get(dp8393xState *s, int width, uint16_t *base,
int offset)
static uint16_t dp8393x_get(dp8393xState *s, int width, int offset)
{
uint16_t val;
if (s->big_endian) {
val = be16_to_cpu(base[offset * width + width - 1]);
val = be16_to_cpu(s->data[offset * width + width - 1]);
} else {
val = le16_to_cpu(base[offset * width]);
val = le16_to_cpu(s->data[offset * width]);
}
return val;
}
static void dp8393x_put(dp8393xState *s, int width, uint16_t *base, int offset,
static void dp8393x_put(dp8393xState *s, int width, int offset,
uint16_t val)
{
if (s->big_endian) {
base[offset * width + width - 1] = cpu_to_be16(val);
s->data[offset * width + width - 1] = cpu_to_be16(val);
} else {
base[offset * width] = cpu_to_le16(val);
s->data[offset * width] = cpu_to_le16(val);
}
}
@ -267,7 +267,6 @@ static void dp8393x_update_irq(dp8393xState *s)
static void dp8393x_do_load_cam(dp8393xState *s)
{
uint16_t data[8];
int width, size;
uint16_t index = 0;
@ -277,13 +276,13 @@ static void dp8393x_do_load_cam(dp8393xState *s)
while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */
address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->cam[index][0] = dp8393x_get(s, width, data, 1) & 0xff;
s->cam[index][1] = dp8393x_get(s, width, data, 1) >> 8;
s->cam[index][2] = dp8393x_get(s, width, data, 2) & 0xff;
s->cam[index][3] = dp8393x_get(s, width, data, 2) >> 8;
s->cam[index][4] = dp8393x_get(s, width, data, 3) & 0xff;
s->cam[index][5] = dp8393x_get(s, width, data, 3) >> 8;
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
s->cam[index][3] = dp8393x_get(s, width, 2) >> 8;
s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff;
s->cam[index][5] = dp8393x_get(s, width, 3) >> 8;
DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
s->cam[index][0], s->cam[index][1], s->cam[index][2],
s->cam[index][3], s->cam[index][4], s->cam[index][5]);
@ -295,8 +294,8 @@ static void dp8393x_do_load_cam(dp8393xState *s)
/* Read CAM enable */
address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->regs[SONIC_CE] = dp8393x_get(s, width, data, 0);
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
/* Done */
@ -307,20 +306,19 @@ static void dp8393x_do_load_cam(dp8393xState *s)
static void dp8393x_do_read_rra(dp8393xState *s)
{
uint16_t data[8];
int width, size;
/* Read memory */
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width;
address_space_rw(&s->as, dp8393x_rrp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
/* Update SONIC registers */
s->regs[SONIC_CRBA0] = dp8393x_get(s, width, data, 0);
s->regs[SONIC_CRBA1] = dp8393x_get(s, width, data, 1);
s->regs[SONIC_RBWC0] = dp8393x_get(s, width, data, 2);
s->regs[SONIC_RBWC1] = dp8393x_get(s, width, data, 3);
s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2);
s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3);
DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
@ -417,7 +415,6 @@ static void dp8393x_do_receiver_disable(dp8393xState *s)
static void dp8393x_do_transmit_packets(dp8393xState *s)
{
NetClientState *nc = qemu_get_queue(s->nic);
uint16_t data[12];
int width, size;
int tx_len, len;
uint16_t i;
@ -429,18 +426,17 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * 6 * width;
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
tx_len = 0;
/* Update registers */
s->regs[SONIC_TCR] = dp8393x_get(s, width, data, 0) & 0xf000;
s->regs[SONIC_TPS] = dp8393x_get(s, width, data, 1);
s->regs[SONIC_TFC] = dp8393x_get(s, width, data, 2);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, data, 3);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, data, 4);
s->regs[SONIC_TFS] = dp8393x_get(s, width, data, 5);
s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000;
s->regs[SONIC_TPS] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFC] = dp8393x_get(s, width, 2);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 5);
/* Handle programmable interrupt */
if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
@ -465,10 +461,10 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
size = sizeof(uint16_t) * 3 * width;
address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, data, 0);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, data, 1);
s->regs[SONIC_TFS] = dp8393x_get(s, width, data, 2);
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
}
}
@ -495,12 +491,12 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
/* Write status */
dp8393x_put(s, width, data, 0,
dp8393x_put(s, width, 0,
s->regs[SONIC_TCR] & 0x0fff); /* status */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as,
dp8393x_ttda(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
@ -509,9 +505,9 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
dp8393x_ttda(s) +
sizeof(uint16_t) *
(4 + 3 * s->regs[SONIC_TFC]) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->regs[SONIC_CTDA] = dp8393x_get(s, width, data, 0) & ~0x1;
if (dp8393x_get(s, width, data, 0) & 0x1) {
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1;
if (dp8393x_get(s, width, 0) & 0x1) {
/* EOL detected */
break;
}
@ -748,7 +744,6 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size_t size)
{
dp8393xState *s = qemu_get_nic_opaque(nc);
uint16_t data[10];
int packet_type;
uint32_t available, address;
int width, rx_len = size;
@ -773,8 +768,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size = sizeof(uint16_t) * 1 * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)data, size, 0);
if (dp8393x_get(s, width, data, 0) & 0x1) {
(uint8_t *)s->data, size, 0);
if (dp8393x_get(s, width, 0) & 0x1) {
/* Still EOL ; stop reception */
return -1;
} else {
@ -818,27 +813,33 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Write status to memory */
DPRINTF("Write status at %08x\n", dp8393x_crda(s));
dp8393x_put(s, width, data, 0, s->regs[SONIC_RCR]); /* status */
dp8393x_put(s, width, data, 1, rx_len); /* byte count */
dp8393x_put(s, width, data, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
dp8393x_put(s, width, data, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
dp8393x_put(s, width, data, 4, s->regs[SONIC_RSC]); /* seq_no */
dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */
dp8393x_put(s, width, 1, rx_len); /* byte count */
dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
size = sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, dp8393x_crda(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1);
/* Move to next descriptor */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, data, 0);
MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */
s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
} else {
dp8393x_put(s, width, data, 0, 0); /* in_use */
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
/* Clear in_use, but it is always 16bit wide */
int offset = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
if (s->big_endian && width == 2) {
/* we need to adjust the offset of the 16bit field */
offset += sizeof(uint16_t);
}
s->data[0] = 0;
address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)s->data, sizeof(uint16_t), 1);
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);