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target-m68k: define ext_opsize 

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170611231633.32582-4-laurent@vivier.eu>
This commit is contained in:
Laurent Vivier 2017-06-12 01:16:29 +02:00
parent c88f8107b1
commit 69e698220f
1 changed files with 24 additions and 19 deletions
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43
target/m68k/translate.c
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@ -669,6 +669,21 @@ static inline int insn_opsize(int insn)
} }
} }
static inline int ext_opsize(int ext, int pos)
{
switch ((ext >> pos) & 7) {
case 0: return OS_LONG;
case 1: return OS_SINGLE;
case 2: return OS_EXTENDED;
case 3: return OS_PACKED;
case 4: return OS_WORD;
case 5: return OS_DOUBLE;
case 6: return OS_BYTE;
default:
g_assert_not_reached();
}
}
/* Assign value to a register. If the width is less than the register width /* Assign value to a register. If the width is less than the register width
only the low part of the register is set. */ only the low part of the register is set. */
static void gen_partset_reg(int opsize, TCGv reg, TCGv val) static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
@ -4111,20 +4126,19 @@ DISAS_INSN(fpu)
tmp32 = tcg_temp_new_i32(); tmp32 = tcg_temp_new_i32();
/* fmove */ /* fmove */
/* ??? TODO: Proper behavior on overflow. */ /* ??? TODO: Proper behavior on overflow. */
switch ((ext >> 10) & 7) {
case 0: opsize = ext_opsize(ext, 10);
opsize = OS_LONG; switch (opsize) {
case OS_LONG:
gen_helper_f64_to_i32(tmp32, cpu_env, src); gen_helper_f64_to_i32(tmp32, cpu_env, src);
break; break;
case 1: case OS_SINGLE:
opsize = OS_SINGLE;
gen_helper_f64_to_f32(tmp32, cpu_env, src); gen_helper_f64_to_f32(tmp32, cpu_env, src);
break; break;
case 4: case OS_WORD:
opsize = OS_WORD;
gen_helper_f64_to_i32(tmp32, cpu_env, src); gen_helper_f64_to_i32(tmp32, cpu_env, src);
break; break;
case 5: /* OS_DOUBLE */ case OS_DOUBLE:
tcg_gen_mov_i32(tmp32, AREG(insn, 0)); tcg_gen_mov_i32(tmp32, AREG(insn, 0));
switch ((insn >> 3) & 7) { switch ((insn >> 3) & 7) {
case 2: case 2:
@ -4153,8 +4167,7 @@ DISAS_INSN(fpu)
} }
tcg_temp_free_i32(tmp32); tcg_temp_free_i32(tmp32);
return; return;
case 6: case OS_BYTE:
opsize = OS_BYTE;
gen_helper_f64_to_i32(tmp32, cpu_env, src); gen_helper_f64_to_i32(tmp32, cpu_env, src);
break; break;
default: default:
@ -4227,15 +4240,7 @@ DISAS_INSN(fpu)
} }
if (ext & (1 << 14)) { if (ext & (1 << 14)) {
/* Source effective address. */ /* Source effective address. */
switch ((ext >> 10) & 7) { opsize = ext_opsize(ext, 10);
case 0: opsize = OS_LONG; break;
case 1: opsize = OS_SINGLE; break;
case 4: opsize = OS_WORD; break;
case 5: opsize = OS_DOUBLE; break;
case 6: opsize = OS_BYTE; break;
default:
goto undef;
}
if (opsize == OS_DOUBLE) { if (opsize == OS_DOUBLE) {
tmp32 = tcg_temp_new_i32(); tmp32 = tcg_temp_new_i32();
tcg_gen_mov_i32(tmp32, AREG(insn, 0)); tcg_gen_mov_i32(tmp32, AREG(insn, 0));