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QOM device refactorings 

* Replace all uses of FROM_SYSBUS() macro with QOM cast macros
   i) "QOM cast cleanup for X"
      Indicates a mechanical 1:1 between TYPE_* and *State.
   ii) "QOM'ify X and Y"
       Indicates abstract types may have been inserted or similar changes
       to type hierarchy.
   ii) Renames
       Coding Style fixes such as CamelCase have been applied in some cases.
 * Fix for sparc floppy - cf. ii) above
 * Change PCI type hierarchy to provide PCI_BRIDGE() casts
 * In doing so, prepare for adopting QOM realize
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Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into staging

QOM device refactorings

* Replace all uses of FROM_SYSBUS() macro with QOM cast macros
  i) "QOM cast cleanup for X"
     Indicates a mechanical 1:1 between TYPE_* and *State.
  ii) "QOM'ify X and Y"
      Indicates abstract types may have been inserted or similar changes
      to type hierarchy.
  ii) Renames
      Coding Style fixes such as CamelCase have been applied in some cases.
* Fix for sparc floppy - cf. ii) above
* Change PCI type hierarchy to provide PCI_BRIDGE() casts
* In doing so, prepare for adopting QOM realize

# gpg: Signature made Mon 29 Jul 2013 02:15:22 PM CDT using RSA key ID 3E7E013F
# gpg: Can't check signature: public key not found

# By Andreas Färber (171) and others
# Via Andreas Färber
* afaerber/tags/qom-devices-for-anthony: (173 commits)
  sysbus: QOM parent field cleanup for SysBusDevice
  spapr_pci: QOM cast cleanup
  ioapic: QOM cast cleanup
  kvm/ioapic: QOM cast cleanup
  kvmvapic: QOM cast cleanup
  mipsnet: QOM cast cleanup
  opencores_eth: QOM cast cleanup
  exynos4210_i2c: QOM cast cleanup
  sysbus: Remove unused sysbus_new() prototype
  sysbus: Drop FROM_SYSBUS()
  xilinx_timer: QOM cast cleanup
  tusb6010: QOM cast cleanup
  slavio_timer: QOM cast cleanup
  pxa2xx_timer: QOM'ify pxa25x-timer and pxa27x-timer
  puv3_ost: QOM cast cleanup
  pl031: QOM cast cleanup
  pl031: Rename pl031_state to PL031State
  milkymist-sysctl: QOM cast cleanup
  m48t59: QOM cast cleanup for M48t59SysBusState
  lm32_timer: QOM cast cleanup
  ...
This commit is contained in:
Anthony Liguori 2013-07-29 14:39:49 -05:00
parent eddbf0ab9d b67964d702
commit 6a4992d0bd
146 changed files with 2509 additions and 1735 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -80,6 +80,7 @@ M: Michael Walle <michael@walle.cc>
S: Maintained
F: target-lm32/
F: hw/lm32/
F: hw/char/lm32_*
M68K
M: Paul Brook <paul@codesourcery.com>

16
hw/arm/armv7m.c
View File

@ -114,15 +114,21 @@ static const MemoryRegionOps bitband_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define TYPE_BITBAND "ARM,bitband-memory"
#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
typedef struct {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t base;
} BitBandState;
static int bitband_init(SysBusDevice *dev)
{
BitBandState *s = FROM_SYSBUS(BitBandState, dev);
BitBandState *s = BITBAND(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &bitband_ops, &s->base,
"bitband", 0x02000000);
@ -134,12 +140,12 @@ static void armv7m_bitband_init(void)
{
DeviceState *dev;
dev = qdev_create(NULL, "ARM,bitband-memory");
dev = qdev_create(NULL, TYPE_BITBAND);
qdev_prop_set_uint32(dev, "base", 0x20000000);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x22000000);
dev = qdev_create(NULL, "ARM,bitband-memory");
dev = qdev_create(NULL, TYPE_BITBAND);
qdev_prop_set_uint32(dev, "base", 0x40000000);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x42000000);
@ -270,7 +276,7 @@ static void bitband_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo bitband_info = {
.name = "ARM,bitband-memory",
.name = TYPE_BITBAND,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(BitBandState),
.class_init = bitband_class_init,

16
hw/arm/highbank.c
View File

@ -116,8 +116,15 @@ static const MemoryRegionOps hb_mem_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
#define HIGHBANK_REGISTERS(obj) \
OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
typedef struct {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion *iomem;
uint32_t regs[NUM_REGS];
} HighbankRegsState;
@ -135,8 +142,7 @@ static VMStateDescription vmstate_highbank_regs = {
static void highbank_regs_reset(DeviceState *dev)
{
SysBusDevice *sys_dev = SYS_BUS_DEVICE(dev);
HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);
HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
s->regs[0x40] = 0x05F20121;
s->regs[0x41] = 0x2;
@ -146,7 +152,7 @@ static void highbank_regs_reset(DeviceState *dev)
static int highbank_regs_init(SysBusDevice *dev)
{
HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
s->iomem = g_new(MemoryRegion, 1);
memory_region_init_io(s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
@ -168,7 +174,7 @@ static void highbank_regs_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo highbank_regs_info = {
.name = "highbank-regs",
.name = TYPE_HIGHBANK_REGISTERS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(HighbankRegsState),
.class_init = highbank_regs_class_init,

76
hw/arm/integratorcp.c
View File

@ -15,8 +15,15 @@
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
typedef struct {
SysBusDevice busdev;
#define TYPE_INTEGRATOR_CM "integrator_core"
#define INTEGRATOR_CM(obj) \
OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
typedef struct IntegratorCMState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t memsz;
MemoryRegion flash;
@ -31,7 +38,7 @@ typedef struct {
uint32_t int_level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
} integratorcm_state;
} IntegratorCMState;
static uint8_t integrator_spd[128] = {
128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
@ -41,7 +48,7 @@ static uint8_t integrator_spd[128] = {
static uint64_t integratorcm_read(void *opaque, hwaddr offset,
unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
IntegratorCMState *s = opaque;
if (offset >= 0x100 && offset < 0x200) {
/* CM_SPD */
if (offset >= 0x180)
@ -108,7 +115,7 @@ static uint64_t integratorcm_read(void *opaque, hwaddr offset,
}
}
static void integratorcm_do_remap(integratorcm_state *s)
static void integratorcm_do_remap(IntegratorCMState *s)
{
/* Sync memory region state with CM_CTRL REMAP bit:
* bit 0 => flash at address 0; bit 1 => RAM
@ -116,7 +123,7 @@ static void integratorcm_do_remap(integratorcm_state *s)
memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
}
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
{
if (value & 8) {
qemu_system_reset_request();
@ -133,7 +140,7 @@ static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
integratorcm_do_remap(s);
}
static void integratorcm_update(integratorcm_state *s)
static void integratorcm_update(IntegratorCMState *s)
{
/* ??? The CPU irq/fiq is raised when either the core module or base PIC
are active. */
@ -144,7 +151,7 @@ static void integratorcm_update(integratorcm_state *s)
static void integratorcm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
IntegratorCMState *s = opaque;
switch (offset >> 2) {
case 2: /* CM_OSC */
if (s->cm_lock == 0xa05f)
@ -226,7 +233,7 @@ static const MemoryRegionOps integratorcm_ops = {
static int integratorcm_init(SysBusDevice *dev)
{
integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
IntegratorCMState *s = INTEGRATOR_CM(dev);
s->cm_osc = 0x01000048;
/* ??? What should the high bits of this value be? */
@ -264,15 +271,21 @@ static int integratorcm_init(SysBusDevice *dev)
/* Integrator/CP hardware emulation. */
/* Primary interrupt controller. */
typedef struct icp_pic_state
{
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
qemu_irq parent_irq;
qemu_irq parent_fiq;
#define TYPE_INTEGRATOR_PIC "integrator_pic"
#define INTEGRATOR_PIC(obj) \
OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
typedef struct icp_pic_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
qemu_irq parent_irq;
qemu_irq parent_fiq;
} icp_pic_state;
static void icp_pic_update(icp_pic_state *s)
@ -367,16 +380,17 @@ static const MemoryRegionOps icp_pic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pic_init(SysBusDevice *dev)
static int icp_pic_init(SysBusDevice *sbd)
{
icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
DeviceState *dev = DEVICE(sbd);
icp_pic_state *s = INTEGRATOR_PIC(dev);
qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_fiq);
qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
sysbus_init_irq(sbd, &s->parent_irq);
sysbus_init_irq(sbd, &s->parent_fiq);
memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s,
"icp-pic", 0x00800000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -474,19 +488,19 @@ static void integratorcp_init(QEMUMachineInitArgs *args)
memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, "integrator_core");
dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
qdev_init_nofail(dev);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
cpu_pic = arm_pic_init_cpu(cpu);
dev = sysbus_create_varargs("integrator_pic", 0x14000000,
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
cpu_pic[ARM_PIC_CPU_IRQ],
cpu_pic[ARM_PIC_CPU_FIQ], NULL);
for (i = 0; i < 32; i++) {
pic[i] = qdev_get_gpio_in(dev, i);
}
sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
sysbus_create_varargs("integrator_pit", 0x13000000,
pic[5], pic[6], pic[7], NULL);
sysbus_create_simple("pl031", 0x15000000, pic[8]);
@ -524,7 +538,7 @@ static void integratorcp_machine_init(void)
machine_init(integratorcp_machine_init);
static Property core_properties[] = {
DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
DEFINE_PROP_END_OF_LIST(),
};
@ -538,9 +552,9 @@ static void core_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo core_info = {
.name = "integrator_core",
.name = TYPE_INTEGRATOR_CM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(integratorcm_state),
.instance_size = sizeof(IntegratorCMState),
.class_init = core_class_init,
};
@ -552,7 +566,7 @@ static void icp_pic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo icp_pic_info = {
.name = "integrator_pic",
.name = TYPE_INTEGRATOR_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(icp_pic_state),
.class_init = icp_pic_class_init,

158
hw/arm/musicpal.c
View File

@ -146,8 +146,15 @@ typedef struct mv88w8618_rx_desc {
uint32_t next;
} mv88w8618_rx_desc;
#define TYPE_MV88W8618_ETH "mv88w8618_eth"
#define MV88W8618_ETH(obj) \
OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH)
typedef struct mv88w8618_eth_state {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
uint32_t smir;
@ -382,16 +389,17 @@ static NetClientInfo net_mv88w8618_info = {
.cleanup = eth_cleanup,
};
static int mv88w8618_eth_init(SysBusDevice *dev)
static int mv88w8618_eth_init(SysBusDevice *sbd)
{
mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
DeviceState *dev = DEVICE(sbd);
mv88w8618_eth_state *s = MV88W8618_ETH(dev);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), dev->id, s);
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_eth_ops, s,
"mv88w8618-eth", MP_ETH_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -429,7 +437,7 @@ static void mv88w8618_eth_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mv88w8618_eth_info = {
.name = "mv88w8618_eth",
.name = TYPE_MV88W8618_ETH,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mv88w8618_eth_state),
.class_init = mv88w8618_eth_class_init,
@ -454,8 +462,15 @@ static const TypeInfo mv88w8618_eth_info = {
#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
#define TYPE_MUSICPAL_LCD "musicpal_lcd"
#define MUSICPAL_LCD(obj) \
OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD)
typedef struct musicpal_lcd_state {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t brightness;
uint32_t mode;
@ -534,7 +549,7 @@ static void lcd_invalidate(void *opaque)
{
}
static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level)
{
musicpal_lcd_state *s = opaque;
s->brightness &= ~(1 << irq);
@ -606,20 +621,21 @@ static const GraphicHwOps musicpal_gfx_ops = {
.gfx_update = lcd_refresh,
};
static int musicpal_lcd_init(SysBusDevice *dev)
static int musicpal_lcd_init(SysBusDevice *sbd)
{
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
DeviceState *dev = DEVICE(sbd);
musicpal_lcd_state *s = MUSICPAL_LCD(dev);
s->brightness = 7;
memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_lcd_ops, s,
"musicpal-lcd", MP_LCD_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
s->con = graphic_console_init(DEVICE(dev), &musicpal_gfx_ops, s);
s->con = graphic_console_init(dev, &musicpal_gfx_ops, s);
qemu_console_resize(s->con, 128*3, 64*3);
qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3);
return 0;
}
@ -650,7 +666,7 @@ static void musicpal_lcd_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo musicpal_lcd_info = {
.name = "musicpal_lcd",
.name = TYPE_MUSICPAL_LCD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(musicpal_lcd_state),
.class_init = musicpal_lcd_class_init,
@ -661,9 +677,15 @@ static const TypeInfo musicpal_lcd_info = {
#define MP_PIC_ENABLE_SET 0x08
#define MP_PIC_ENABLE_CLR 0x0C
typedef struct mv88w8618_pic_state
{
SysBusDevice busdev;
#define TYPE_MV88W8618_PIC "mv88w8618_pic"
#define MV88W8618_PIC(obj) \
OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC)
typedef struct mv88w8618_pic_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t level;
uint32_t enabled;
@ -721,8 +743,7 @@ static void mv88w8618_pic_write(void *opaque, hwaddr offset,
static void mv88w8618_pic_reset(DeviceState *d)
{
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
SYS_BUS_DEVICE(d));
mv88w8618_pic_state *s = MV88W8618_PIC(d);
s->level = 0;
s->enabled = 0;
@ -736,9 +757,9 @@ static const MemoryRegionOps mv88w8618_pic_ops = {
static int mv88w8618_pic_init(SysBusDevice *dev)
{
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
mv88w8618_pic_state *s = MV88W8618_PIC(dev);
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_pic_ops, s,
"musicpal-pic", MP_PIC_SIZE);
@ -769,7 +790,7 @@ static void mv88w8618_pic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mv88w8618_pic_info = {
.name = "mv88w8618_pic",
.name = TYPE_MV88W8618_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mv88w8618_pic_state),
.class_init = mv88w8618_pic_class_init,
@ -795,8 +816,15 @@ typedef struct mv88w8618_timer_state {
qemu_irq irq;
} mv88w8618_timer_state;
#define TYPE_MV88W8618_PIT "mv88w8618_pit"
#define MV88W8618_PIT(obj) \
OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT)
typedef struct mv88w8618_pit_state {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
mv88w8618_timer_state timer[4];
} mv88w8618_pit_state;
@ -878,8 +906,7 @@ static void mv88w8618_pit_write(void *opaque, hwaddr offset,
static void mv88w8618_pit_reset(DeviceState *d)
{
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
SYS_BUS_DEVICE(d));
mv88w8618_pit_state *s = MV88W8618_PIT(d);
int i;
for (i = 0; i < 4; i++) {
@ -896,7 +923,7 @@ static const MemoryRegionOps mv88w8618_pit_ops = {
static int mv88w8618_pit_init(SysBusDevice *dev)
{
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
mv88w8618_pit_state *s = MV88W8618_PIT(dev);
int i;
/* Letting them all run at 1 MHz is likely just a pragmatic
@ -946,7 +973,7 @@ static void mv88w8618_pit_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mv88w8618_pit_info = {
.name = "mv88w8618_pit",
.name = TYPE_MV88W8618_PIT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mv88w8618_pit_state),
.class_init = mv88w8618_pit_class_init,
@ -955,8 +982,15 @@ static const TypeInfo mv88w8618_pit_info = {
/* Flash config register offsets */
#define MP_FLASHCFG_CFGR0 0x04
#define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
#define MV88W8618_FLASHCFG(obj) \
OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG)
typedef struct mv88w8618_flashcfg_state {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t cfgr0;
} mv88w8618_flashcfg_state;
@ -996,7 +1030,7 @@ static const MemoryRegionOps mv88w8618_flashcfg_ops = {
static int mv88w8618_flashcfg_init(SysBusDevice *dev)
{
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev);
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
memory_region_init_io(&s->iomem, OBJECT(s), &mv88w8618_flashcfg_ops, s,
@ -1026,7 +1060,7 @@ static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mv88w8618_flashcfg_info = {
.name = "mv88w8618_flashcfg",
.name = TYPE_MV88W8618_FLASHCFG,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mv88w8618_flashcfg_state),
.class_init = mv88w8618_flashcfg_class_init,
@ -1149,8 +1183,15 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
/* LCD brightness bits in GPIO_OE_HI */
#define MP_OE_LCD_BRIGHTNESS 0x0007
#define TYPE_MUSICPAL_GPIO "musicpal_gpio"
#define MUSICPAL_GPIO(obj) \
OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO)
typedef struct musicpal_gpio_state {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t lcd_brightness;
uint32_t out_state;
@ -1310,8 +1351,7 @@ static const MemoryRegionOps musicpal_gpio_ops = {
static void musicpal_gpio_reset(DeviceState *d)
{
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
SYS_BUS_DEVICE(d));
musicpal_gpio_state *s = MUSICPAL_GPIO(d);
s->lcd_brightness = 0;
s->out_state = 0;
@ -1321,19 +1361,20 @@ static void musicpal_gpio_reset(DeviceState *d)
s->isr = 0;
}
static int musicpal_gpio_init(SysBusDevice *dev)
static int musicpal_gpio_init(SysBusDevice *sbd)
{
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
DeviceState *dev = DEVICE(sbd);
musicpal_gpio_state *s = MUSICPAL_GPIO(dev);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_gpio_ops, s,
"musicpal-gpio", MP_GPIO_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out));
qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32);
return 0;
}
@ -1365,7 +1406,7 @@ static void musicpal_gpio_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo musicpal_gpio_info = {
.name = "musicpal_gpio",
.name = TYPE_MUSICPAL_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(musicpal_gpio_state),
.class_init = musicpal_gpio_class_init,
@ -1395,8 +1436,15 @@ static const TypeInfo musicpal_gpio_info = {
#define MP_KEY_BTN_VOLUME (1 << 6)
#define MP_KEY_BTN_NAVIGATION (1 << 7)
#define TYPE_MUSICPAL_KEY "musicpal_key"
#define MUSICPAL_KEY(obj) \
OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY)
typedef struct musicpal_key_state {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t kbd_extended;
uint32_t pressed_keys;
@ -1480,17 +1528,18 @@ static void musicpal_key_event(void *opaque, int keycode)
s->kbd_extended = 0;
}
static int musicpal_key_init(SysBusDevice *dev)
static int musicpal_key_init(SysBusDevice *sbd)
{
musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
DeviceState *dev = DEVICE(sbd);
musicpal_key_state *s = MUSICPAL_KEY(dev);
memory_region_init(&s->iomem, OBJECT(s), "dummy", 0);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
s->kbd_extended = 0;
s->pressed_keys = 0;
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out));
qemu_add_kbd_event_handler(musicpal_key_event, s);
@ -1519,7 +1568,7 @@ static void musicpal_key_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo musicpal_key_info = {
.name = "musicpal_key",
.name = TYPE_MUSICPAL_KEY,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(musicpal_key_state),
.class_init = musicpal_key_class_init,
@ -1572,12 +1621,12 @@ static void musicpal_init(QEMUMachineInitArgs *args)
vmstate_register_ram_global(sram);
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
cpu_pic[ARM_PIC_CPU_IRQ]);
for (i = 0; i < 32; i++) {
pic[i] = qdev_get_gpio_in(dev, i);
}
sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
pic[MP_TIMER4_IRQ], NULL);
@ -1624,10 +1673,10 @@ static void musicpal_init(QEMUMachineInitArgs *args)
#endif
}
sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL);
qemu_check_nic_model(&nd_table[0], "mv88w8618");
dev = qdev_create(NULL, "mv88w8618_eth");
dev = qdev_create(NULL, TYPE_MV88W8618_ETH);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
@ -1637,12 +1686,13 @@ static void musicpal_init(QEMUMachineInitArgs *args)
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
pic[MP_GPIO_IRQ]);
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL);
key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL);
/* I2C read data */
qdev_connect_gpio_out(i2c_dev, 0,

79
hw/arm/pxa2xx.c
View File

@ -457,9 +457,16 @@ static const VMStateDescription vmstate_pxa2xx_mm = {
}
};
#define TYPE_PXA2XX_SSP "pxa2xx-ssp"
#define PXA2XX_SSP(obj) \
OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
/* Synchronous Serial Ports */
typedef struct {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
int enable;
@ -757,19 +764,20 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
static int pxa2xx_ssp_init(SysBusDevice *dev)
static int pxa2xx_ssp_init(SysBusDevice *sbd)
{
PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
DeviceState *dev = DEVICE(sbd);
PXA2xxSSPState *s = PXA2XX_SSP(dev);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
"pxa2xx-ssp", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
sysbus_init_mmio(sbd, &s->iomem);
register_savevm(dev, "pxa2xx_ssp", -1, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
s->bus = ssi_create_bus(&dev->qdev, "ssi");
s->bus = ssi_create_bus(dev, "ssi");
return 0;
}
@ -790,8 +798,15 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
#define TYPE_PXA2XX_RTC "pxa2xx_rtc"
#define PXA2XX_RTC(obj) \
OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
typedef struct {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t rttr;
uint32_t rtsr;
@ -1102,7 +1117,7 @@ static const MemoryRegionOps pxa2xx_rtc_ops = {
static int pxa2xx_rtc_init(SysBusDevice *dev)
{
PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
PXA2xxRTCState *s = PXA2XX_RTC(dev);
struct tm tm;
int wom;
@ -1197,7 +1212,7 @@ static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pxa2xx_rtc_sysbus_info = {
.name = "pxa2xx_rtc",
.name = TYPE_PXA2XX_RTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxRTCState),
.class_init = pxa2xx_rtc_sysbus_class_init,
@ -1209,8 +1224,15 @@ typedef struct {
PXA2xxI2CState *host;
} PXA2xxI2CSlaveState;
#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
#define PXA2XX_I2C(obj) \
OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
struct PXA2xxI2CState {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
PXA2xxI2CSlaveState *slave;
i2c_bus *bus;
@ -1458,16 +1480,16 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
SysBusDevice *i2c_dev;
PXA2xxI2CState *s;
i2c_dev = SYS_BUS_DEVICE(qdev_create(NULL, "pxa2xx_i2c"));
qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
qdev_prop_set_uint32(&i2c_dev->qdev, "offset", base & region_size);
qdev_init_nofail(&i2c_dev->qdev);
dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
qdev_prop_set_uint32(dev, "size", region_size + 1);
qdev_prop_set_uint32(dev, "offset", base & region_size);
qdev_init_nofail(dev);
i2c_dev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
sysbus_connect_irq(i2c_dev, 0, irq);
s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
s = PXA2XX_I2C(i2c_dev);
/* FIXME: Should the slave device really be on a separate bus? */
dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE(dev));
@ -1476,16 +1498,17 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
return s;
}
static int pxa2xx_i2c_initfn(SysBusDevice *dev)
static int pxa2xx_i2c_initfn(SysBusDevice *sbd)
{
PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
DeviceState *dev = DEVICE(sbd);
PXA2xxI2CState *s = PXA2XX_I2C(dev);
s->bus = i2c_init_bus(&dev->qdev, "i2c");
s->bus = i2c_init_bus(dev, "i2c");
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
"pxa2xx-i2c", s->region_size);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
return 0;
}
@ -1513,7 +1536,7 @@ static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pxa2xx_i2c_info = {
.name = "pxa2xx_i2c",
.name = TYPE_PXA2XX_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxI2CState),
.class_init = pxa2xx_i2c_class_init,
@ -2107,7 +2130,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
DeviceState *dev;
dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
@ -2120,7 +2143,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
sysbus_create_simple("pxa2xx_rtc", 0x40900000,
sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
s->i2c[0] = pxa2xx_i2c_init(0x40301600,
@ -2238,7 +2261,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
for (i = 0; pxa255_ssp[i].io_base; i ++) {
DeviceState *dev;
dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
@ -2251,7 +2274,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
sysbus_create_simple("pxa2xx_rtc", 0x40900000,
sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
s->i2c[0] = pxa2xx_i2c_init(0x40301600,
@ -2278,7 +2301,7 @@ static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pxa2xx_ssp_info = {
.name = "pxa2xx-ssp",
.name = TYPE_PXA2XX_SSP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxSSPState),
.class_init = pxa2xx_ssp_class_init,

35
hw/arm/pxa2xx_gpio.c
View File

@ -13,9 +13,16 @@
#define PXA2XX_GPIO_BANKS 4
#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
#define PXA2XX_GPIO(obj) \
OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq0, irq1, irqX;
int lines;
@ -256,7 +263,7 @@ DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUState *cs = CPU(cpu);
DeviceState *dev;
dev = qdev_create(NULL, "pxa2xx-gpio");
dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
qdev_prop_set_int32(dev, "lines", lines);
qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
qdev_init_nofail(dev);
@ -272,22 +279,21 @@ DeviceState *pxa2xx_gpio_init(hwaddr base,
return dev;
}
static int pxa2xx_gpio_initfn(SysBusDevice *dev)
static int pxa2xx_gpio_initfn(SysBusDevice *sbd)
{
PXA2xxGPIOInfo *s;
s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
DeviceState *dev = DEVICE(sbd);
PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
qdev_init_gpio_out(dev, s->handler, s->lines);
memory_region_init_io(&s->iomem, OBJECT(s), &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq0);
sysbus_init_irq(dev, &s->irq1);
sysbus_init_irq(dev, &s->irqX);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq0);
sysbus_init_irq(sbd, &s->irq1);
sysbus_init_irq(sbd, &s->irqX);
return 0;
}
@ -298,7 +304,8 @@ static int pxa2xx_gpio_initfn(SysBusDevice *dev)
*/
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, SYS_BUS_DEVICE(dev));
PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
s->read_notify = handler;
}
@ -337,7 +344,7 @@ static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pxa2xx_gpio_info = {
.name = "pxa2xx-gpio",
.name = TYPE_PXA2XX_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxGPIOInfo),
.class_init = pxa2xx_gpio_class_init,

18
hw/arm/pxa2xx_pic.c
View File

@ -31,8 +31,15 @@
#define PXA2XX_PIC_SRCS 40
#define TYPE_PXA2XX_PIC "pxa2xx_pic"
#define PXA2XX_PIC(obj) \
OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC)
typedef struct {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
ARMCPU *cpu;
uint32_t int_enabled[2];
@ -260,9 +267,8 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, SYS_BUS_DEVICE(dev));
DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC);
PXA2xxPICState *s = PXA2XX_PIC(dev);
s->cpu = cpu;
@ -284,7 +290,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
/* Enable IC coprocessor access. */
define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s);
define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
return dev;
}
@ -321,7 +327,7 @@ static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pxa2xx_pic_info = {
.name = "pxa2xx_pic",
.name = TYPE_PXA2XX_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxPICState),
.class_init = pxa2xx_pic_class_init,

41
hw/arm/spitz.c
View File

@ -50,8 +50,12 @@
#define FLASHCTL_RYBY (1 << 5)
#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
#define TYPE_SL_NAND "sl-nand"
#define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
DeviceState *nand;
uint8_t ctl;
@ -147,7 +151,7 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
{
DeviceState *dev;
dev = qdev_create(NULL, "sl-nand");
dev = qdev_create(NULL, TYPE_SL_NAND);
qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
if (size == FLASH_128M)
@ -159,12 +163,11 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
}
static int sl_nand_init(SysBusDevice *dev) {
SLNANDState *s;
static int sl_nand_init(SysBusDevice *dev)
{
SLNANDState *s = SL_NAND(dev);
DriveInfo *nand;
s = FROM_SYSBUS(SLNANDState, dev);
s->ctl = 0;
nand = drive_get(IF_MTD, 0, 0);
s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id);
@ -212,8 +215,13 @@ static const int spitz_gpiomap[5] = {
SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
};
#define TYPE_SPITZ_KEYBOARD "spitz-keyboard"
#define SPITZ_KEYBOARD(obj) \
OBJECT_CHECK(SpitzKeyboardState, (obj), TYPE_SPITZ_KEYBOARD)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
qemu_irq sense[SPITZ_KEY_SENSE_NUM];
qemu_irq gpiomap[5];
int keymap[0x80];
@ -458,8 +466,8 @@ static void spitz_keyboard_register(PXA2xxState *cpu)
DeviceState *dev;
SpitzKeyboardState *s;
dev = sysbus_create_simple("spitz-keyboard", -1, NULL);
s = FROM_SYSBUS(SpitzKeyboardState, SYS_BUS_DEVICE(dev));
dev = sysbus_create_simple(TYPE_SPITZ_KEYBOARD, -1, NULL);
s = SPITZ_KEYBOARD(dev);
for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
@ -482,13 +490,12 @@ static void spitz_keyboard_register(PXA2xxState *cpu)
qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
}
static int spitz_keyboard_init(SysBusDevice *dev)
static int spitz_keyboard_init(SysBusDevice *sbd)
{
SpitzKeyboardState *s;
DeviceState *dev = DEVICE(sbd);
SpitzKeyboardState *s = SPITZ_KEYBOARD(dev);
int i, j;
s = FROM_SYSBUS(SpitzKeyboardState, dev);
for (i = 0; i < 0x80; i ++)
s->keymap[i] = -1;
for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
@ -499,8 +506,8 @@ static int spitz_keyboard_init(SysBusDevice *dev)
spitz_keyboard_pre_map(s);
s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);
qdev_init_gpio_in(dev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
qdev_init_gpio_out(dev, s->sense, SPITZ_KEY_SENSE_NUM);
return 0;
}
@ -1027,7 +1034,7 @@ static void sl_nand_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sl_nand_info = {
.name = "sl-nand",
.name = TYPE_SL_NAND,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SLNANDState),
.class_init = sl_nand_class_init,
@ -1062,7 +1069,7 @@ static void spitz_keyboard_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo spitz_keyboard_info = {
.name = "spitz-keyboard",
.name = TYPE_SPITZ_KEYBOARD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SpitzKeyboardState),
.class_init = spitz_keyboard_class_init,

75
hw/arm/stellaris.c
View File

@ -43,8 +43,13 @@ typedef const struct {
/* General purpose timer module. */
#define TYPE_STELLARIS_GPTM "stellaris-gptm"
#define STELLARIS_GPTM(obj) \
OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
typedef struct gptm_state {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t config;
uint32_t mode[2];
@ -300,21 +305,22 @@ static const VMStateDescription vmstate_stellaris_gptm = {
}
};
static int stellaris_gptm_init(SysBusDevice *dev)
static int stellaris_gptm_init(SysBusDevice *sbd)
{
gptm_state *s = FROM_SYSBUS(gptm_state, dev);
DeviceState *dev = DEVICE(sbd);
gptm_state *s = STELLARIS_GPTM(dev);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_out(dev, &s->trigger, 1);
memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s,
"gptm", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
s->opaque[0] = s->opaque[1] = s;
s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]);
vmstate_register(&dev->qdev, -1, &vmstate_stellaris_gptm, s);
vmstate_register(dev, -1, &vmstate_stellaris_gptm, s);
return 0;
}
@ -679,8 +685,13 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
/* I2C controller. */
#define TYPE_STELLARIS_I2C "stellaris-i2c"
#define STELLARIS_I2C(obj) \
OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
i2c_bus *bus;
qemu_irq irq;
MemoryRegion iomem;
@ -853,21 +864,22 @@ static const VMStateDescription vmstate_stellaris_i2c = {
}
};
static int stellaris_i2c_init(SysBusDevice * dev)
static int stellaris_i2c_init(SysBusDevice *sbd)
{
stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev);
DeviceState *dev = DEVICE(sbd);
stellaris_i2c_state *s = STELLARIS_I2C(dev);
i2c_bus *bus;
sysbus_init_irq(dev, &s->irq);
bus = i2c_init_bus(&dev->qdev, "i2c");
sysbus_init_irq(sbd, &s->irq);
bus = i2c_init_bus(dev, "i2c");
s->bus = bus;
memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s,
"i2c", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
/* ??? For now we only implement the master interface. */
stellaris_i2c_reset(s);
vmstate_register(&dev->qdev, -1, &vmstate_stellaris_i2c, s);
vmstate_register(dev, -1, &vmstate_stellaris_i2c, s);
return 0;
}
@ -885,9 +897,13 @@ static int stellaris_i2c_init(SysBusDevice * dev)
#define STELLARIS_ADC_FIFO_EMPTY 0x0100
#define STELLARIS_ADC_FIFO_FULL 0x1000
typedef struct
{
SysBusDevice busdev;
#define TYPE_STELLARIS_ADC "stellaris-adc"
#define STELLARIS_ADC(obj) \
OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
typedef struct StellarisADCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t actss;
uint32_t ris;
@ -1136,21 +1152,22 @@ static const VMStateDescription vmstate_stellaris_adc = {
}
};
static int stellaris_adc_init(SysBusDevice *dev)
static int stellaris_adc_init(SysBusDevice *sbd)
{
stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev);
DeviceState *dev = DEVICE(sbd);
stellaris_adc_state *s = STELLARIS_ADC(dev);
int n;
for (n = 0; n < 4; n++) {
sysbus_init_irq(dev, &s->irq[n]);
sysbus_init_irq(sbd, &s->irq[n]);
}
memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s,
"adc", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
stellaris_adc_reset(s);
qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
vmstate_register(&dev->qdev, -1, &vmstate_stellaris_adc, s);
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
vmstate_register(dev, -1, &vmstate_stellaris_adc, s);
return 0;
}
@ -1207,7 +1224,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
flash_size, sram_size, kernel_filename, cpu_model);
if (board->dc1 & (1 << 16)) {
dev = sysbus_create_varargs("stellaris-adc", 0x40038000,
dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
pic[14], pic[15], pic[16], pic[17], NULL);
adc = qdev_get_gpio_in(dev, 0);
} else {
@ -1215,7 +1232,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
}
for (i = 0; i < 4; i++) {
if (board->dc2 & (0x10000 << i)) {
dev = sysbus_create_simple("stellaris-gptm",
dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
0x40030000 + i * 0x1000,
pic[timer_irq[i]]);
/* TODO: This is incorrect, but we get away with it because
@ -1238,7 +1255,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
}
if (board->dc2 & (1 << 12)) {
dev = sysbus_create_simple("stellaris-i2c", 0x40020000, pic[8]);
dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]);
i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
if (board->peripherals & BP_OLED_I2C) {
i2c_create_slave(i2c, "ssd0303", 0x3d);
@ -1357,7 +1374,7 @@ static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo stellaris_i2c_info = {
.name = "stellaris-i2c",
.name = TYPE_STELLARIS_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(stellaris_i2c_state),
.class_init = stellaris_i2c_class_init,
@ -1371,7 +1388,7 @@ static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo stellaris_gptm_info = {
.name = "stellaris-gptm",
.name = TYPE_STELLARIS_GPTM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(gptm_state),
.class_init = stellaris_gptm_class_init,
@ -1385,7 +1402,7 @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo stellaris_adc_info = {
.name = "stellaris-adc",
.name = TYPE_STELLARIS_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(stellaris_adc_state),
.class_init = stellaris_adc_class_init,

134
hw/arm/strongarm.c
View File

@ -70,8 +70,14 @@ static struct {
};
/* Interrupt Controller */
typedef struct {
SysBusDevice busdev;
#define TYPE_STRONGARM_PIC "strongarm_pic"
#define STRONGARM_PIC(obj) \
OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
typedef struct StrongARMPICState {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
qemu_irq fiq;
@ -168,16 +174,17 @@ static const MemoryRegionOps strongarm_pic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int strongarm_pic_initfn(SysBusDevice *dev)
static int strongarm_pic_initfn(SysBusDevice *sbd)
{
StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
DeviceState *dev = DEVICE(sbd);
StrongARMPICState *s = STRONGARM_PIC(dev);
qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_pic_ops, s,
"pic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->fiq);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->fiq);
return 0;
}
@ -214,7 +221,7 @@ static void strongarm_pic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo strongarm_pic_info = {
.name = "strongarm_pic",
.name = TYPE_STRONGARM_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMPICState),
.class_init = strongarm_pic_class_init,
@ -235,8 +242,13 @@ static const TypeInfo strongarm_pic_info = {
* trim delete isn't emulated, so
* f = 32 768 / (RTTR_trim + 1) */
typedef struct {
SysBusDevice busdev;
#define TYPE_STRONGARM_RTC "strongarm-rtc"
#define STRONGARM_RTC(obj) \
OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
typedef struct StrongARMRTCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t rttr;
uint32_t rtsr;
@ -367,7 +379,7 @@ static const MemoryRegionOps strongarm_rtc_ops = {
static int strongarm_rtc_init(SysBusDevice *dev)
{
StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
StrongARMRTCState *s = STRONGARM_RTC(dev);
struct tm tm;
s->rttr = 0x0;
@ -436,7 +448,7 @@ static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo strongarm_rtc_sysbus_info = {
.name = "strongarm-rtc",
.name = TYPE_STRONGARM_RTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMRTCState),
.class_init = strongarm_rtc_sysbus_class_init,
@ -452,6 +464,10 @@ static const TypeInfo strongarm_rtc_sysbus_info = {
#define GEDR 0x18
#define GAFR 0x1c
#define TYPE_STRONGARM_GPIO "strongarm-gpio"
#define STRONGARM_GPIO(obj) \
OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
struct StrongARMGPIOInfo {
SysBusDevice busdev;
@ -618,7 +634,7 @@ static DeviceState *strongarm_gpio_init(hwaddr base,
DeviceState *dev;
int i;
dev = qdev_create(NULL, "strongarm-gpio");
dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
@ -629,24 +645,23 @@ static DeviceState *strongarm_gpio_init(hwaddr base,
return dev;
}
static int strongarm_gpio_initfn(SysBusDevice *dev)
static int strongarm_gpio_initfn(SysBusDevice *sbd)
{
StrongARMGPIOInfo *s;
DeviceState *dev = DEVICE(sbd);
StrongARMGPIOInfo *s = STRONGARM_GPIO(dev);
int i;
s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
qdev_init_gpio_out(&dev->qdev, s->handler, 28);
qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
qdev_init_gpio_out(dev, s->handler, 28);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_gpio_ops, s,
"gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
for (i = 0; i < 11; i++) {
sysbus_init_irq(dev, &s->irqs[i]);
sysbus_init_irq(sbd, &s->irqs[i]);
}
sysbus_init_irq(dev, &s->irqX);
sysbus_init_irq(sbd, &s->irqX);
return 0;
}
@ -678,7 +693,7 @@ static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo strongarm_gpio_info = {
.name = "strongarm-gpio",
.name = TYPE_STRONGARM_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMGPIOInfo),
.class_init = strongarm_gpio_class_init,
@ -691,9 +706,14 @@ static const TypeInfo strongarm_gpio_info = {
#define PSDR 0x0c
#define PPFR 0x10
#define TYPE_STRONGARM_PPC "strongarm-ppc"
#define STRONGARM_PPC(obj) \
OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
typedef struct StrongARMPPCInfo StrongARMPPCInfo;
struct StrongARMPPCInfo {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq handler[28];
@ -802,19 +822,18 @@ static const MemoryRegionOps strongarm_ppc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int strongarm_ppc_init(SysBusDevice *dev)
static int strongarm_ppc_init(SysBusDevice *sbd)
{
StrongARMPPCInfo *s;
DeviceState *dev = DEVICE(sbd);
StrongARMPPCInfo *s = STRONGARM_PPC(dev);
s = FROM_SYSBUS(StrongARMPPCInfo, dev);
qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
qdev_init_gpio_out(&dev->qdev, s->handler, 22);
qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
qdev_init_gpio_out(dev, s->handler, 22);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ppc_ops, s,
"ppc", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -845,7 +864,7 @@ static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo strongarm_ppc_info = {
.name = "strongarm-ppc",
.name = TYPE_STRONGARM_PPC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMPPCInfo),
.class_init = strongarm_ppc_class_init,
@ -889,8 +908,13 @@ static const TypeInfo strongarm_ppc_info = {
#define RX_FIFO_FRE (1 << 9)
#define RX_FIFO_ROR (1 << 10)
typedef struct {
SysBusDevice busdev;
#define TYPE_STRONGARM_UART "strongarm-uart"
#define STRONGARM_UART(obj) \
OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
typedef struct StrongARMUARTState {
SysBusDevice parent_obj;
MemoryRegion iomem;
CharDriverState *chr;
qemu_irq irq;
@ -1206,7 +1230,7 @@ static const MemoryRegionOps strongarm_uart_ops = {
static int strongarm_uart_init(SysBusDevice *dev)
{
StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
StrongARMUARTState *s = STRONGARM_UART(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_uart_ops, s,
"uart", 0x10000);
@ -1229,7 +1253,7 @@ static int strongarm_uart_init(SysBusDevice *dev)
static void strongarm_uart_reset(DeviceState *dev)
{
StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
StrongARMUARTState *s = STRONGARM_UART(dev);
s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
s->brd = 23; /* 9600 */
@ -1305,15 +1329,21 @@ static void strongarm_uart_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo strongarm_uart_info = {
.name = "strongarm-uart",
.name = TYPE_STRONGARM_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMUARTState),
.class_init = strongarm_uart_class_init,
};
/* Synchronous Serial Ports */
typedef struct {
SysBusDevice busdev;
#define TYPE_STRONGARM_SSP "strongarm-ssp"
#define STRONGARM_SSP(obj) \
OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
typedef struct StrongARMSSPState {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
SSIBus *bus;
@ -1495,23 +1525,25 @@ static int strongarm_ssp_post_load(void *opaque, int version_id)
return 0;
}
static int strongarm_ssp_init(SysBusDevice *dev)
static int strongarm_ssp_init(SysBusDevice *sbd)
{
StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
DeviceState *dev = DEVICE(sbd);
StrongARMSSPState *s = STRONGARM_SSP(dev);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &strongarm_ssp_ops, s,
"ssp", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
s->bus = ssi_create_bus(&dev->qdev, "ssi");
s->bus = ssi_create_bus(dev, "ssi");
return 0;
}
static void strongarm_ssp_reset(DeviceState *dev)
{
StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
StrongARMSSPState *s = STRONGARM_SSP(dev);
s->sssr = 0x03; /* 3 bit data, SPI, disabled */
s->rx_start = 0;
s->rx_level = 0;
@ -1545,7 +1577,7 @@ static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo strongarm_ssp_info = {
.name = "strongarm-ssp",
.name = TYPE_STRONGARM_SSP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(StrongARMSSPState),
.class_init = strongarm_ssp_class_init,
@ -1592,15 +1624,15 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
NULL);
sysbus_create_simple("strongarm-rtc", 0x90010000,
sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
s->gpio = strongarm_gpio_init(0x90040000, s->pic);
s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
for (i = 0; sa_serial[i].io_base; i++) {
DeviceState *dev = qdev_create(NULL, "strongarm-uart");
DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
@ -1609,7 +1641,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
qdev_get_gpio_in(s->pic, sa_serial[i].irq));
}
s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");

37
hw/arm/versatilepb.c
View File

@ -25,15 +25,19 @@
/* Primary interrupt controller. */
typedef struct vpb_sic_state
{
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t level;
uint32_t mask;
uint32_t pic_enable;
qemu_irq parent[32];
int irq;
#define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
#define VERSATILE_PB_SIC(obj) \
OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)
typedef struct vpb_sic_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t level;
uint32_t mask;
uint32_t pic_enable;
qemu_irq parent[32];
int irq;
} vpb_sic_state;
static const VMStateDescription vmstate_vpb_sic = {
@ -144,19 +148,20 @@ static const MemoryRegionOps vpb_sic_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int vpb_sic_init(SysBusDevice *dev)
static int vpb_sic_init(SysBusDevice *sbd)
{
vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
DeviceState *dev = DEVICE(sbd);
vpb_sic_state *s = VERSATILE_PB_SIC(dev);
int i;
qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
qdev_init_gpio_in(dev, vpb_sic_set_irq, 32);
for (i = 0; i < 32; i++) {
sysbus_init_irq(dev, &s->parent[i]);
sysbus_init_irq(sbd, &s->parent[i]);
}
s->irq = 31;
memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s,
"vpb-sic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -213,7 +218,7 @@ static void versatile_init(QEMUMachineInitArgs *args, int board_id)
for (n = 0; n < 32; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL);
for (n = 0; n < 32; n++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
sic[n] = qdev_get_gpio_in(dev, n);
@ -393,7 +398,7 @@ static void vpb_sic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo vpb_sic_info = {
.name = "versatilepb_sic",
.name = TYPE_VERSATILE_PB_SIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(vpb_sic_state),
.class_init = vpb_sic_class_init,

15
hw/audio/cs4231.c
View File

@ -33,8 +33,13 @@
#define CS_DREGS 32
#define CS_MAXDREG (CS_DREGS - 1)
#define TYPE_CS4231 "SUNW,CS4231"
#define CS4231(obj) \
OBJECT_CHECK(CSState, (obj), TYPE_CS4231)
typedef struct CSState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
uint32_t regs[CS_REGS];
@ -47,7 +52,7 @@ typedef struct CSState {
static void cs_reset(DeviceState *d)
{
CSState *s = container_of(d, CSState, busdev.qdev);
CSState *s = CS4231(d);
memset(s->regs, 0, CS_REGS * 4);
memset(s->dregs, 0, CS_DREGS);
@ -111,7 +116,7 @@ static void cs_mem_write(void *opaque, hwaddr addr,
break;
case 4:
if (val & 1) {
cs_reset(&s->busdev.qdev);
cs_reset(DEVICE(s));
}
val &= 0x7f;
s->regs[saddr] = val;
@ -142,7 +147,7 @@ static const VMStateDescription vmstate_cs4231 = {
static int cs4231_init1(SysBusDevice *dev)
{
CSState *s = FROM_SYSBUS(CSState, dev);
CSState *s = CS4231(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &cs_mem_ops, s, "cs4321",
CS_SIZE);
@ -168,7 +173,7 @@ static void cs4231_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo cs4231_info = {
.name = "SUNW,CS4231",
.name = TYPE_CS4231,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(CSState),
.class_init = cs4231_class_init,

14
hw/audio/marvell_88w8618.c
View File

@ -36,8 +36,13 @@
#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
#define MP_AUDIO_MONO (1 << 14)
#define TYPE_MV88W8618_AUDIO "mv88w8618_audio"
#define MV88W8618_AUDIO(obj) \
OBJECT_CHECK(mv88w8618_audio_state, (obj), TYPE_MV88W8618_AUDIO)
typedef struct mv88w8618_audio_state {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
uint32_t playback_mode;
@ -219,8 +224,7 @@ static void mv88w8618_audio_write(void *opaque, hwaddr offset,
static void mv88w8618_audio_reset(DeviceState *d)
{
mv88w8618_audio_state *s = FROM_SYSBUS(mv88w8618_audio_state,
SYS_BUS_DEVICE(d));
mv88w8618_audio_state *s = MV88W8618_AUDIO(d);
s->playback_mode = 0;
s->status = 0;
@ -238,7 +242,7 @@ static const MemoryRegionOps mv88w8618_audio_ops = {
static int mv88w8618_audio_init(SysBusDevice *dev)
{
mv88w8618_audio_state *s = FROM_SYSBUS(mv88w8618_audio_state, dev);
mv88w8618_audio_state *s = MV88W8618_AUDIO(dev);
sysbus_init_irq(dev, &s->irq);
@ -287,7 +291,7 @@ static void mv88w8618_audio_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mv88w8618_audio_info = {
.name = "mv88w8618_audio",
.name = TYPE_MV88W8618_AUDIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mv88w8618_audio_state),
.class_init = mv88w8618_audio_class_init,

13
hw/audio/milkymist-ac97.c
View File

@ -51,8 +51,13 @@ enum {
CTRL_EN = (1<<0),
};
#define TYPE_MILKYMIST_AC97 "milkymist-ac97"
#define MILKYMIST_AC97(obj) \
OBJECT_CHECK(MilkymistAC97State, (obj), TYPE_MILKYMIST_AC97)
struct MilkymistAC97State {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion regs_region;
QEMUSoundCard card;
@ -258,7 +263,7 @@ static void ac97_out_cb(void *opaque, int free_b)
static void milkymist_ac97_reset(DeviceState *d)
{
MilkymistAC97State *s = container_of(d, MilkymistAC97State, busdev.qdev);
MilkymistAC97State *s = MILKYMIST_AC97(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -280,7 +285,7 @@ static int ac97_post_load(void *opaque, int version_id)
static int milkymist_ac97_init(SysBusDevice *dev)
{
MilkymistAC97State *s = FROM_SYSBUS(typeof(*s), dev);
MilkymistAC97State *s = MILKYMIST_AC97(dev);
struct audsettings as;
sysbus_init_irq(dev, &s->crrequest_irq);
@ -330,7 +335,7 @@ static void milkymist_ac97_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_ac97_info = {
.name = "milkymist-ac97",
.name = TYPE_MILKYMIST_AC97,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistAC97State),
.class_init = milkymist_ac97_class_init,

45
hw/audio/pl041.c
View File

@ -70,8 +70,12 @@ typedef struct {
uint8_t rx_sample_size;
} pl041_channel;
typedef struct {
SysBusDevice busdev;
#define TYPE_PL041 "pl041"
#define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041)
typedef struct PL041State {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
@ -80,7 +84,7 @@ typedef struct {
pl041_regfile regs;
pl041_channel fifo1;
lm4549_state codec;
} pl041_state;
} PL041State;
static const unsigned char pl041_default_id[8] = {
@ -107,7 +111,7 @@ static const char *get_reg_name(hwaddr offset)
}
#endif
static uint8_t pl041_compute_periphid3(pl041_state *s)
static uint8_t pl041_compute_periphid3(PL041State *s)
{
uint8_t id3 = 1; /* One channel */
@ -142,7 +146,7 @@ static uint8_t pl041_compute_periphid3(pl041_state *s)
return id3;
}
static void pl041_reset(pl041_state *s)
static void pl041_reset(PL041State *s)
{
DBG_L1("pl041_reset\n");
@ -156,7 +160,7 @@ static void pl041_reset(pl041_state *s)
}
static void pl041_fifo1_write(pl041_state *s, uint32_t value)
static void pl041_fifo1_write(PL041State *s, uint32_t value)
{
pl041_channel *channel = &s->fifo1;
pl041_fifo *fifo = &s->fifo1.tx_fifo;
@ -239,7 +243,7 @@ static void pl041_fifo1_write(pl041_state *s, uint32_t value)
DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
}
static void pl041_fifo1_transmit(pl041_state *s)
static void pl041_fifo1_transmit(PL041State *s)
{
pl041_channel *channel = &s->fifo1;
pl041_fifo *fifo = &s->fifo1.tx_fifo;
@ -291,7 +295,7 @@ static void pl041_fifo1_transmit(pl041_state *s)
}
}
static void pl041_isr1_update(pl041_state *s)
static void pl041_isr1_update(PL041State *s)
{
/* Update ISR1 */
if (s->regs.sr1 & TXUNDERRUN) {
@ -320,7 +324,7 @@ static void pl041_isr1_update(pl041_state *s)
static void pl041_request_data(void *opaque)
{
pl041_state *s = (pl041_state *)opaque;
PL041State *s = (PL041State *)opaque;
/* Trigger pending transfers */
pl041_fifo1_transmit(s);
@ -330,7 +334,7 @@ static void pl041_request_data(void *opaque)
static uint64_t pl041_read(void *opaque, hwaddr offset,
unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
PL041State *s = (PL041State *)opaque;
int value;
if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
@ -364,7 +368,7 @@ static uint64_t pl041_read(void *opaque, hwaddr offset,
static void pl041_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
PL041State *s = (PL041State *)opaque;
uint16_t control, data;
uint32_t result;
@ -504,7 +508,7 @@ static void pl041_write(void *opaque, hwaddr offset,
static void pl041_device_reset(DeviceState *d)
{
pl041_state *s = DO_UPCAST(pl041_state, busdev.qdev, d);
PL041State *s = PL041(d);
pl041_reset(s);
}
@ -517,7 +521,7 @@ static const MemoryRegionOps pl041_ops = {
static int pl041_init(SysBusDevice *dev)
{
pl041_state *s = FROM_SYSBUS(pl041_state, dev);
PL041State *s = PL041(dev);
DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);
@ -603,12 +607,12 @@ static const VMStateDescription vmstate_pl041 = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(fifo_depth, pl041_state),
VMSTATE_STRUCT(regs, pl041_state, 0,
VMSTATE_UINT32(fifo_depth, PL041State),
VMSTATE_STRUCT(regs, PL041State, 0,
vmstate_pl041_regfile, pl041_regfile),
VMSTATE_STRUCT(fifo1, pl041_state, 0,
VMSTATE_STRUCT(fifo1, PL041State, 0,
vmstate_pl041_channel, pl041_channel),
VMSTATE_STRUCT(codec, pl041_state, 0,
VMSTATE_STRUCT(codec, PL041State, 0,
vmstate_lm4549_state, lm4549_state),
VMSTATE_END_OF_LIST()
}
@ -616,7 +620,8 @@ static const VMStateDescription vmstate_pl041 = {
static Property pl041_device_properties[] = {
/* Non-compact FIFO depth property */
DEFINE_PROP_UINT32("nc_fifo_depth", pl041_state, fifo_depth, DEFAULT_FIFO_DEPTH),
DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth,
DEFAULT_FIFO_DEPTH),
DEFINE_PROP_END_OF_LIST(),
};
@ -634,9 +639,9 @@ static void pl041_device_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pl041_device_info = {
.name = "pl041",
.name = TYPE_PL041,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl041_state),
.instance_size = sizeof(PL041State),
.class_init = pl041_device_class_init,
};

94
hw/block/fdc.c
View File

@ -544,7 +544,7 @@ struct FDCtrl {
uint8_t timer1;
};
#define TYPE_SYSBUS_FDC "sysbus-fdc"
#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
typedef struct FDCtrlSysBus {
@ -2055,7 +2055,7 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
SysBusDevice *sbd;
FDCtrlSysBus *sys;
dev = qdev_create(NULL, TYPE_SYSBUS_FDC);
dev = qdev_create(NULL, "sysbus-fdc");
sys = SYSBUS_FDC(dev);
fdctrl = &sys->state;
fdctrl->dma_chann = dma_chann; /* FIXME */
@ -2153,60 +2153,49 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
static void sysbus_fdc_initfn(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
FDCtrlSysBus *sys = SYSBUS_FDC(obj);
FDCtrl *fdctrl = &sys->state;
memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
"fdc", 0x08);
}
static void sysbus_fdc_realize(DeviceState *dev, Error **errp)
{
FDCtrlSysBus *sys = SYSBUS_FDC(dev);
FDCtrl *fdctrl = &sys->state;
SysBusDevice *b = SYS_BUS_DEVICE(dev);
Error *err = NULL;
sysbus_init_mmio(b, &fdctrl->iomem);
sysbus_init_irq(b, &fdctrl->irq);
qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
fdctrl->dma_chann = -1;
qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
fdctrl_realize_common(fdctrl, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
"fdc", 0x08);
sysbus_init_mmio(sbd, &fdctrl->iomem);
}
static void sun4m_fdc_initfn(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
FDCtrlSysBus *sys = SYSBUS_FDC(obj);
FDCtrl *fdctrl = &sys->state;
fdctrl->sun4m = 1;
memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
fdctrl, "fdctrl", 0x08);
sysbus_init_mmio(sbd, &fdctrl->iomem);
}
static void sun4m_fdc_realize(DeviceState *dev, Error **errp)
static void sysbus_fdc_common_initfn(Object *obj)
{
DeviceState *dev = DEVICE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
FDCtrlSysBus *sys = SYSBUS_FDC(obj);
FDCtrl *fdctrl = &sys->state;
qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
sysbus_init_irq(sbd, &fdctrl->irq);
qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
}
static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
{
FDCtrlSysBus *sys = SYSBUS_FDC(dev);
FDCtrl *fdctrl = &sys->state;
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Error *err = NULL;
sysbus_init_mmio(sbd, &fdctrl->iomem);
sysbus_init_irq(sbd, &fdctrl->irq);
qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
fdctrl->sun4m = 1;
qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
fdctrl_realize_common(fdctrl, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
fdctrl_realize_common(fdctrl, errp);
}
FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
@ -2279,17 +2268,13 @@ static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = sysbus_fdc_realize;
dc->reset = fdctrl_external_reset_sysbus;
dc->vmsd = &vmstate_sysbus_fdc;
dc->props = sysbus_fdc_properties;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
static const TypeInfo sysbus_fdc_info = {
.name = TYPE_SYSBUS_FDC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FDCtrlSysBus),
.name = "sysbus-fdc",
.parent = TYPE_SYSBUS_FDC,
.instance_init = sysbus_fdc_initfn,
.class_init = sysbus_fdc_class_init,
};
@ -2303,24 +2288,39 @@ static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = sun4m_fdc_realize;
dc->reset = fdctrl_external_reset_sysbus;
dc->vmsd = &vmstate_sysbus_fdc;
dc->props = sun4m_fdc_properties;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
static const TypeInfo sun4m_fdc_info = {
.name = "SUNW,fdtwo",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FDCtrlSysBus),
.parent = TYPE_SYSBUS_FDC,
.instance_init = sun4m_fdc_initfn,
.class_init = sun4m_fdc_class_init,
};
static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = sysbus_fdc_common_realize;
dc->reset = fdctrl_external_reset_sysbus;
dc->vmsd = &vmstate_sysbus_fdc;
}
static const TypeInfo sysbus_fdc_type_info = {
.name = TYPE_SYSBUS_FDC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FDCtrlSysBus),
.instance_init = sysbus_fdc_common_initfn,
.abstract = true,
.class_init = sysbus_fdc_common_class_init,
};
static void fdc_register_types(void)
{
type_register_static(&isa_fdc_info);
type_register_static(&sysbus_fdc_type_info);
type_register_static(&sysbus_fdc_info);
type_register_static(&sun4m_fdc_info);
}

30
hw/block/onenand.c
View File

@ -34,8 +34,12 @@
/* Fixed */
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
typedef struct {
SysBusDevice busdev;
#define TYPE_ONE_NAND "onenand"
#define ONE_NAND(obj) OBJECT_CHECK(OneNANDState, (obj), TYPE_ONE_NAND)
typedef struct OneNANDState {
SysBusDevice parent_obj;
struct {
uint16_t man;
uint16_t dev;
@ -226,7 +230,9 @@ static void onenand_reset(OneNANDState *s, int cold)
static void onenand_system_reset(DeviceState *dev)
{
onenand_reset(FROM_SYSBUS(OneNANDState, SYS_BUS_DEVICE(dev)), 1);
OneNANDState *s = ONE_NAND(dev);
onenand_reset(s, 1);
}
static inline int onenand_load_main(OneNANDState *s, int sec, int secn,
@ -757,11 +763,13 @@ static const MemoryRegionOps onenand_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int onenand_initfn(SysBusDevice *dev)
static int onenand_initfn(SysBusDevice *sbd)
{
OneNANDState *s = (OneNANDState *)dev;
DeviceState *dev = DEVICE(sbd);
OneNANDState *s = ONE_NAND(dev);
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
void *ram;
s->base = (hwaddr)-1;
s->rdy = NULL;
s->blocks = size >> BLOCK_SHIFT;
@ -794,9 +802,9 @@ static int onenand_initfn(SysBusDevice *dev)
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
onenand_mem_setup(s);
sysbus_init_irq(dev, &s->intr);
sysbus_init_mmio(dev, &s->container);
vmstate_register(&dev->qdev,
sysbus_init_irq(sbd, &s->intr);
sysbus_init_mmio(sbd, &s->container);
vmstate_register(dev,
((s->shift & 0x7f) << 24)
| ((s->id.man & 0xff) << 16)
| ((s->id.dev & 0xff) << 8)
@ -825,7 +833,7 @@ static void onenand_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo onenand_info = {
.name = "onenand",
.name = TYPE_ONE_NAND,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OneNANDState),
.class_init = onenand_class_init,
@ -838,7 +846,9 @@ static void onenand_register_types(void)
void *onenand_raw_otp(DeviceState *onenand_device)
{
return FROM_SYSBUS(OneNANDState, SYS_BUS_DEVICE(onenand_device))->otp;
OneNANDState *s = ONE_NAND(onenand_device);
return s->otp;
}
type_init(onenand_register_types)

10
hw/char/cadence_uart.c
View File

@ -106,8 +106,12 @@
#define R_MAX (R_TTRIG + 1)
#define TYPE_CADENCE_UART "cadence_uart"
#define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t r[R_MAX];
uint8_t r_fifo[RX_FIFO_SIZE];
@ -442,7 +446,7 @@ static void cadence_uart_reset(UartState *s)
static int cadence_uart_init(SysBusDevice *dev)
{
UartState *s = FROM_SYSBUS(UartState, dev);
UartState *s = CADENCE_UART(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
@ -504,7 +508,7 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo cadence_uart_info = {
.name = "cadence_uart",
.name = TYPE_CADENCE_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(UartState),
.class_init = cadence_uart_class_init,

19
hw/char/escc.c
View File

@ -96,8 +96,11 @@ typedef struct ChannelState {
uint8_t rx, tx;
} ChannelState;
#define ESCC(obj) OBJECT_CHECK(ESCCState, (obj), TYPE_ESCC)
typedef struct ESCCState {
SysBusDevice busdev;
SysBusDevice parent_obj;
struct ChannelState chn[2];
uint32_t it_shift;
MemoryRegion mmio;
@ -309,7 +312,7 @@ static void escc_reset_chn(ChannelState *s)
static void escc_reset(DeviceState *d)
{
ESCCState *s = container_of(d, ESCCState, busdev.qdev);
ESCCState *s = ESCC(d);
escc_reset_chn(&s->chn[0]);
escc_reset_chn(&s->chn[1]);
@ -534,7 +537,7 @@ static void escc_mem_write(void *opaque, hwaddr addr,
escc_reset_chn(&serial->chn[1]);
return;
case MINTR_RST_ALL:
escc_reset(&serial->busdev.qdev);
escc_reset(DEVICE(serial));
return;
}
break;
@ -691,7 +694,7 @@ MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
SysBusDevice *s;
ESCCState *d;
dev = qdev_create(NULL, "escc");
dev = qdev_create(NULL, TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", 0);
qdev_prop_set_uint32(dev, "frequency", clock);
qdev_prop_set_uint32(dev, "it_shift", it_shift);
@ -707,7 +710,7 @@ MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
sysbus_mmio_map(s, 0, base);
}
d = FROM_SYSBUS(ESCCState, s);
d = ESCC(s);
return &d->mmio;
}
@ -852,7 +855,7 @@ void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
DeviceState *dev;
SysBusDevice *s;
dev = qdev_create(NULL, "escc");
dev = qdev_create(NULL, TYPE_ESCC);
qdev_prop_set_uint32(dev, "disabled", disabled);
qdev_prop_set_uint32(dev, "frequency", clock);
qdev_prop_set_uint32(dev, "it_shift", it_shift);
@ -869,7 +872,7 @@ void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
static int escc_init1(SysBusDevice *dev)
{
ESCCState *s = FROM_SYSBUS(ESCCState, dev);
ESCCState *s = ESCC(dev);
unsigned int i;
s->chn[0].disabled = s->disabled;
@ -924,7 +927,7 @@ static void escc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo escc_info = {
.name = "escc",
.name = TYPE_ESCC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ESCCState),
.class_init = escc_class_init,

37
hw/char/etraxfs_ser.c
View File

@ -44,9 +44,13 @@
#define STAT_TR_IDLE 22
#define STAT_TR_RDY 24
struct etrax_serial
{
SysBusDevice busdev;
#define TYPE_ETRAX_FS_SERIAL "etraxfs,serial"
#define ETRAX_SERIAL(obj) \
OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL)
typedef struct ETRAXSerial {
SysBusDevice parent_obj;
MemoryRegion mmio;
CharDriverState *chr;
qemu_irq irq;
@ -59,9 +63,9 @@ struct etrax_serial
/* Control registers. */
uint32_t regs[R_MAX];
};
} ETRAXSerial;
static void ser_update_irq(struct etrax_serial *s)
static void ser_update_irq(ETRAXSerial *s)
{
if (s->rx_fifo_len) {
@ -77,7 +81,7 @@ static void ser_update_irq(struct etrax_serial *s)
static uint64_t
ser_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_serial *s = opaque;
ETRAXSerial *s = opaque;
uint32_t r = 0;
addr >>= 2;
@ -112,7 +116,7 @@ static void
ser_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_serial *s = opaque;
ETRAXSerial *s = opaque;
uint32_t value = val64;
unsigned char ch = val64;
@ -156,7 +160,7 @@ static const MemoryRegionOps ser_ops = {
static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
struct etrax_serial *s = opaque;
ETRAXSerial *s = opaque;
int i;
/* Got a byte. */
@ -177,7 +181,7 @@ static void serial_receive(void *opaque, const uint8_t *buf, int size)
static int serial_can_receive(void *opaque)
{
struct etrax_serial *s = opaque;
ETRAXSerial *s = opaque;
int r;
/* Is the receiver enabled? */
@ -196,7 +200,7 @@ static void serial_event(void *opaque, int event)
static void etraxfs_ser_reset(DeviceState *d)
{
struct etrax_serial *s = container_of(d, typeof(*s), busdev.qdev);
ETRAXSerial *s = ETRAX_SERIAL(d);
/* transmitter begins ready and idle. */
s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
@ -208,7 +212,7 @@ static void etraxfs_ser_reset(DeviceState *d)
static int etraxfs_ser_init(SysBusDevice *dev)
{
struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
ETRAXSerial *s = ETRAX_SERIAL(dev);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->mmio, OBJECT(s), &ser_ops, s,
@ -216,10 +220,11 @@ static int etraxfs_ser_init(SysBusDevice *dev)
sysbus_init_mmio(dev, &s->mmio);
s->chr = qemu_char_get_next_serial();
if (s->chr)
if (s->chr) {
qemu_chr_add_handlers(s->chr,
serial_can_receive, serial_receive,
serial_event, s);
serial_can_receive, serial_receive,
serial_event, s);
}
return 0;
}
@ -233,9 +238,9 @@ static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo etraxfs_ser_info = {
.name = "etraxfs,serial",
.name = TYPE_ETRAX_FS_SERIAL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct etrax_serial),
.instance_size = sizeof(ETRAXSerial),
.class_init = etraxfs_ser_class_init,
};

26
hw/char/exynos4210_uart.c
View File

@ -166,8 +166,13 @@ typedef struct {
uint32_t size;
} Exynos4210UartFIFO;
typedef struct {
SysBusDevice busdev;
#define TYPE_EXYNOS4210_UART "exynos4210.uart"
#define EXYNOS4210_UART(obj) \
OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
typedef struct Exynos4210UartState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
@ -538,8 +543,7 @@ static void exynos4210_uart_event(void *opaque, int event)
static void exynos4210_uart_reset(DeviceState *dev)
{
Exynos4210UartState *s =
container_of(dev, Exynos4210UartState, busdev.qdev);
Exynos4210UartState *s = EXYNOS4210_UART(dev);
int regs_number = sizeof(exynos4210_uart_regs)/sizeof(Exynos4210UartReg);
int i;
@ -582,10 +586,10 @@ static const VMStateDescription vmstate_exynos4210_uart = {
};
DeviceState *exynos4210_uart_create(hwaddr addr,
int fifo_size,
int channel,
CharDriverState *chr,
qemu_irq irq)
int fifo_size,
int channel,
CharDriverState *chr,
qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *bus;
@ -593,7 +597,7 @@ DeviceState *exynos4210_uart_create(hwaddr addr,
const char chr_name[] = "serial";
char label[ARRAY_SIZE(chr_name) + 1];
dev = qdev_create(NULL, "exynos4210.uart");
dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
if (!chr) {
if (channel >= MAX_SERIAL_PORTS) {
@ -627,7 +631,7 @@ DeviceState *exynos4210_uart_create(hwaddr addr,
static int exynos4210_uart_init(SysBusDevice *dev)
{
Exynos4210UartState *s = FROM_SYSBUS(Exynos4210UartState, dev);
Exynos4210UartState *s = EXYNOS4210_UART(dev);
/* memory mapping */
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s,
@ -662,7 +666,7 @@ static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo exynos4210_uart_info = {
.name = "exynos4210.uart",
.name = TYPE_EXYNOS4210_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210UartState),
.class_init = exynos4210_uart_class_init,

13
hw/char/grlib_apbuart.c
View File

@ -67,8 +67,13 @@
#define FIFO_LENGTH 1024
#define TYPE_GRLIB_APB_UART "grlib,apbuart"
#define GRLIB_APB_UART(obj) \
OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)
typedef struct UART {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
@ -232,7 +237,7 @@ static const MemoryRegionOps grlib_apbuart_ops = {
static int grlib_apbuart_init(SysBusDevice *dev)
{
UART *uart = FROM_SYSBUS(typeof(*uart), dev);
UART *uart = GRLIB_APB_UART(dev);
qemu_chr_add_handlers(uart->chr,
grlib_apbuart_can_receive,
@ -252,7 +257,7 @@ static int grlib_apbuart_init(SysBusDevice *dev)
static void grlib_apbuart_reset(DeviceState *d)
{
UART *uart = container_of(d, UART, busdev.qdev);
UART *uart = GRLIB_APB_UART(d);
/* Transmitter FIFO and shift registers are always empty in QEMU */
uart->status = UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY;
@ -279,7 +284,7 @@ static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo grlib_apbuart_info = {
.name = "grlib,apbuart",
.name = TYPE_GRLIB_APB_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(UART),
.class_init = grlib_apbuart_class_init,

16
hw/char/imx_serial.c
View File

@ -43,8 +43,12 @@ do { printf("imx_serial: " fmt , ##args); } while (0)
# define IPRINTF(fmt, args...) do {} while (0)
#endif
typedef struct {
SysBusDevice busdev;
#define TYPE_IMX_SERIAL "imx-serial"
#define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)
typedef struct IMXSerialState {
SysBusDevice parent_obj;
MemoryRegion iomem;
int32_t readbuff;
@ -169,7 +173,7 @@ static void imx_serial_reset(IMXSerialState *s)
static void imx_serial_reset_at_boot(DeviceState *dev)
{
IMXSerialState *s = container_of(dev, IMXSerialState, busdev.qdev);
IMXSerialState *s = IMX_SERIAL(dev);
imx_serial_reset(s);
@ -383,7 +387,7 @@ static const struct MemoryRegionOps imx_serial_ops = {
static int imx_serial_init(SysBusDevice *dev)
{
IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev);
IMXSerialState *s = IMX_SERIAL(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s,
@ -410,7 +414,7 @@ void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
const char chr_name[] = "serial";
char label[ARRAY_SIZE(chr_name) + 1];
dev = qdev_create(NULL, "imx-serial");
dev = qdev_create(NULL, TYPE_IMX_SERIAL);
if (uart >= MAX_SERIAL_PORTS) {
hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
@ -455,7 +459,7 @@ static void imx_serial_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo imx_serial_info = {
.name = "imx-serial",
.name = TYPE_IMX_SERIAL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMXSerialState),
.class_init = imx_serial_class_init,

21
hw/char/lm32_juart.c
View File

@ -22,7 +22,7 @@
#include "trace.h"
#include "sysemu/char.h"
#include "hw/lm32/lm32_juart.h"
#include "hw/char/lm32_juart.h"
enum {
LM32_JUART_MIN_SAVE_VERSION = 0,
@ -38,8 +38,11 @@ enum {
JRX_FULL = (1<<8),
};
#define LM32_JUART(obj) OBJECT_CHECK(LM32JuartState, (obj), TYPE_LM32_JUART)
struct LM32JuartState {
SysBusDevice busdev;
SysBusDevice parent_obj;
CharDriverState *chr;
uint32_t jtx;
@ -49,7 +52,7 @@ typedef struct LM32JuartState LM32JuartState;
uint32_t lm32_juart_get_jtx(DeviceState *d)
{
LM32JuartState *s = container_of(d, LM32JuartState, busdev.qdev);
LM32JuartState *s = LM32_JUART(d);
trace_lm32_juart_get_jtx(s->jtx);
return s->jtx;
@ -57,7 +60,7 @@ uint32_t lm32_juart_get_jtx(DeviceState *d)
uint32_t lm32_juart_get_jrx(DeviceState *d)
{
LM32JuartState *s = container_of(d, LM32JuartState, busdev.qdev);
LM32JuartState *s = LM32_JUART(d);
trace_lm32_juart_get_jrx(s->jrx);
return s->jrx;
@ -65,7 +68,7 @@ uint32_t lm32_juart_get_jrx(DeviceState *d)
void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx)
{
LM32JuartState *s = container_of(d, LM32JuartState, busdev.qdev);
LM32JuartState *s = LM32_JUART(d);
unsigned char ch = jtx & 0xff;
trace_lm32_juart_set_jtx(s->jtx);
@ -78,7 +81,7 @@ void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx)
void lm32_juart_set_jrx(DeviceState *d, uint32_t jtx)
{
LM32JuartState *s = container_of(d, LM32JuartState, busdev.qdev);
LM32JuartState *s = LM32_JUART(d);
trace_lm32_juart_set_jrx(s->jrx);
s->jrx &= ~JRX_FULL;
@ -104,7 +107,7 @@ static void juart_event(void *opaque, int event)
static void juart_reset(DeviceState *d)
{
LM32JuartState *s = container_of(d, LM32JuartState, busdev.qdev);
LM32JuartState *s = LM32_JUART(d);
s->jtx = 0;
s->jrx = 0;
@ -112,7 +115,7 @@ static void juart_reset(DeviceState *d)
static int lm32_juart_init(SysBusDevice *dev)
{
LM32JuartState *s = FROM_SYSBUS(typeof(*s), dev);
LM32JuartState *s = LM32_JUART(dev);
s->chr = qemu_char_get_next_serial();
if (s->chr) {
@ -145,7 +148,7 @@ static void lm32_juart_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo lm32_juart_info = {
.name = "lm32-juart",
.name = TYPE_LM32_JUART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LM32JuartState),
.class_init = lm32_juart_class_init,

12
hw/char/lm32_uart.c
View File

@ -89,8 +89,12 @@ enum {
MSR_DCD = (1<<7),
};
#define TYPE_LM32_UART "lm32-uart"
#define LM32_UART(obj) OBJECT_CHECK(LM32UartState, (obj), TYPE_LM32_UART)
struct LM32UartState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
CharDriverState *chr;
qemu_irq irq;
@ -233,7 +237,7 @@ static void uart_event(void *opaque, int event)
static void uart_reset(DeviceState *d)
{
LM32UartState *s = container_of(d, LM32UartState, busdev.qdev);
LM32UartState *s = LM32_UART(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -246,7 +250,7 @@ static void uart_reset(DeviceState *d)
static int lm32_uart_init(SysBusDevice *dev)
{
LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
LM32UartState *s = LM32_UART(dev);
sysbus_init_irq(dev, &s->irq);
@ -284,7 +288,7 @@ static void lm32_uart_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo lm32_uart_info = {
.name = "lm32-uart",
.name = TYPE_LM32_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LM32UartState),
.class_init = lm32_uart_class_init,

15
hw/char/milkymist-uart.c
View File

@ -52,8 +52,13 @@ enum {
DBG_BREAK_EN = (1<<0),
};
#define TYPE_MILKYMIST_UART "milkymist-uart"
#define MILKYMIST_UART(obj) \
OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART)
struct MilkymistUartState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion regs_region;
CharDriverState *chr;
qemu_irq irq;
@ -179,7 +184,7 @@ static void uart_event(void *opaque, int event)
static void milkymist_uart_reset(DeviceState *d)
{
MilkymistUartState *s = container_of(d, MilkymistUartState, busdev.qdev);
MilkymistUartState *s = MILKYMIST_UART(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -192,12 +197,12 @@ static void milkymist_uart_reset(DeviceState *d)
static int milkymist_uart_init(SysBusDevice *dev)
{
MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
MilkymistUartState *s = MILKYMIST_UART(dev);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
"milkymist-uart", R_MAX * 4);
"milkymist-uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
s->chr = qemu_char_get_next_serial();
@ -230,7 +235,7 @@ static void milkymist_uart_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_uart_info = {
.name = "milkymist-uart",
.name = TYPE_MILKYMIST_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistUartState),
.class_init = milkymist_uart_class_init,

110
hw/char/pl011.c
View File

@ -10,8 +10,12 @@
#include "hw/sysbus.h"
#include "sysemu/char.h"
typedef struct {
SysBusDevice busdev;
#define TYPE_PL011 "pl011"
#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
typedef struct PL011State {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t readbuff;
uint32_t flags;
@ -31,7 +35,7 @@ typedef struct {
CharDriverState *chr;
qemu_irq irq;
const unsigned char *id;
} pl011_state;
} PL011State;
#define PL011_INT_TX 0x20
#define PL011_INT_RX 0x10
@ -46,7 +50,7 @@ static const unsigned char pl011_id_arm[8] =
static const unsigned char pl011_id_luminary[8] =
{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
static void pl011_update(pl011_state *s)
static void pl011_update(PL011State *s)
{
uint32_t flags;
@ -57,7 +61,7 @@ static void pl011_update(pl011_state *s)
static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
PL011State *s = (PL011State *)opaque;
uint32_t c;
if (offset >= 0xfe0 && offset < 0x1000) {
@ -113,7 +117,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
}
}
static void pl011_set_read_trigger(pl011_state *s)
static void pl011_set_read_trigger(PL011State *s)
{
#if 0
/* The docs say the RX interrupt is triggered when the FIFO exceeds
@ -130,7 +134,7 @@ static void pl011_set_read_trigger(pl011_state *s)
static void pl011_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
PL011State *s = (PL011State *)opaque;
unsigned char ch;
switch (offset >> 2) {
@ -191,7 +195,7 @@ static void pl011_write(void *opaque, hwaddr offset,
static int pl011_can_receive(void *opaque)
{
pl011_state *s = (pl011_state *)opaque;
PL011State *s = (PL011State *)opaque;
if (s->lcr & 0x10)
return s->read_count < 16;
@ -201,7 +205,7 @@ static int pl011_can_receive(void *opaque)
static void pl011_put_fifo(void *opaque, uint32_t value)
{
pl011_state *s = (pl011_state *)opaque;
PL011State *s = (PL011State *)opaque;
int slot;
slot = s->read_pos + s->read_count;
@ -242,83 +246,81 @@ static const VMStateDescription vmstate_pl011 = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(readbuff, pl011_state),
VMSTATE_UINT32(flags, pl011_state),
VMSTATE_UINT32(lcr, pl011_state),
VMSTATE_UINT32(cr, pl011_state),
VMSTATE_UINT32(dmacr, pl011_state),
VMSTATE_UINT32(int_enabled, pl011_state),
VMSTATE_UINT32(int_level, pl011_state),
VMSTATE_UINT32_ARRAY(read_fifo, pl011_state, 16),
VMSTATE_UINT32(ilpr, pl011_state),
VMSTATE_UINT32(ibrd, pl011_state),
VMSTATE_UINT32(fbrd, pl011_state),
VMSTATE_UINT32(ifl, pl011_state),
VMSTATE_INT32(read_pos, pl011_state),
VMSTATE_INT32(read_count, pl011_state),
VMSTATE_INT32(read_trigger, pl011_state),
VMSTATE_UINT32(readbuff, PL011State),
VMSTATE_UINT32(flags, PL011State),
VMSTATE_UINT32(lcr, PL011State),
VMSTATE_UINT32(cr, PL011State),
VMSTATE_UINT32(dmacr, PL011State),
VMSTATE_UINT32(int_enabled, PL011State),
VMSTATE_UINT32(int_level, PL011State),
VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
VMSTATE_UINT32(ilpr, PL011State),
VMSTATE_UINT32(ibrd, PL011State),
VMSTATE_UINT32(fbrd, PL011State),
VMSTATE_UINT32(ifl, PL011State),
VMSTATE_INT32(read_pos, PL011State),
VMSTATE_INT32(read_count, PL011State),
VMSTATE_INT32(read_trigger, PL011State),
VMSTATE_END_OF_LIST()
}
};
static int pl011_init(SysBusDevice *dev, const unsigned char *id)
static void pl011_init(Object *obj)
{
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PL011State *s = PL011(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->id = id;
s->chr = qemu_char_get_next_serial();
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
s->read_trigger = 1;
s->ifl = 0x12;
s->cr = 0x300;
s->flags = 0x90;
s->id = pl011_id_arm;
}
static void pl011_realize(DeviceState *dev, Error **errp)
{
PL011State *s = PL011(dev);
s->chr = qemu_char_get_next_serial();
if (s->chr) {
qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
vmstate_register(&dev->qdev, -1, &vmstate_pl011, s);
return 0;
}
static int pl011_arm_init(SysBusDevice *dev)
static void pl011_class_init(ObjectClass *oc, void *data)
{
return pl011_init(dev, pl011_id_arm);
}
DeviceClass *dc = DEVICE_CLASS(oc);
static int pl011_luminary_init(SysBusDevice *dev)
{
return pl011_init(dev, pl011_id_luminary);
}
static void pl011_arm_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = pl011_arm_init;
dc->realize = pl011_realize;
dc->vmsd = &vmstate_pl011;
}
static const TypeInfo pl011_arm_info = {
.name = "pl011",
.name = TYPE_PL011,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl011_state),
.class_init = pl011_arm_class_init,
.instance_size = sizeof(PL011State),
.instance_init = pl011_init,
.class_init = pl011_class_init,
};
static void pl011_luminary_class_init(ObjectClass *klass, void *data)
static void pl011_luminary_init(Object *obj)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
PL011State *s = PL011(obj);
sdc->init = pl011_luminary_init;
s->id = pl011_id_luminary;
}
static const TypeInfo pl011_luminary_info = {
.name = "pl011_luminary",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl011_state),
.class_init = pl011_luminary_class_init,
.parent = TYPE_PL011,
.instance_init = pl011_luminary_init,
};
static void pl011_register_types(void)

30
hw/char/xilinx_uartlite.c
View File

@ -46,9 +46,13 @@
#define CONTROL_RST_RX 0x02
#define CONTROL_IE 0x10
struct xlx_uartlite
{
SysBusDevice busdev;
#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
#define XILINX_UARTLITE(obj) \
OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE)
typedef struct XilinxUARTLite {
SysBusDevice parent_obj;
MemoryRegion mmio;
CharDriverState *chr;
qemu_irq irq;
@ -58,9 +62,9 @@ struct xlx_uartlite
unsigned int rx_fifo_len;
uint32_t regs[R_MAX];
};
} XilinxUARTLite;
static void uart_update_irq(struct xlx_uartlite *s)
static void uart_update_irq(XilinxUARTLite *s)
{
unsigned int irq;
@ -71,7 +75,7 @@ static void uart_update_irq(struct xlx_uartlite *s)
qemu_set_irq(s->irq, irq);
}
static void uart_update_status(struct xlx_uartlite *s)
static void uart_update_status(XilinxUARTLite *s)
{
uint32_t r;
@ -86,7 +90,7 @@ static void uart_update_status(struct xlx_uartlite *s)
static uint64_t
uart_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_uartlite *s = opaque;
XilinxUARTLite *s = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr)
@ -113,7 +117,7 @@ static void
uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_uartlite *s = opaque;
XilinxUARTLite *s = opaque;
uint32_t value = val64;
unsigned char ch = value;
@ -164,7 +168,7 @@ static const MemoryRegionOps uart_ops = {
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
struct xlx_uartlite *s = opaque;
XilinxUARTLite *s = opaque;
/* Got a byte. */
if (s->rx_fifo_len >= 8) {
@ -182,7 +186,7 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
static int uart_can_rx(void *opaque)
{
struct xlx_uartlite *s = opaque;
XilinxUARTLite *s = opaque;
return s->rx_fifo_len < sizeof(s->rx_fifo);
}
@ -194,7 +198,7 @@ static void uart_event(void *opaque, int event)
static int xilinx_uartlite_init(SysBusDevice *dev)
{
struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
XilinxUARTLite *s = XILINX_UARTLITE(dev);
sysbus_init_irq(dev, &s->irq);
@ -217,9 +221,9 @@ static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo xilinx_uartlite_info = {
.name = "xlnx.xps-uartlite",
.name = TYPE_XILINX_UARTLITE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof (struct xlx_uartlite),
.instance_size = sizeof(XilinxUARTLite),
.class_init = xilinx_uartlite_class_init,
};

14
hw/core/empty_slot.c
View File

@ -22,8 +22,12 @@
#define DPRINTF(fmt, ...) do {} while (0)
#endif
#define TYPE_EMPTY_SLOT "empty_slot"
#define EMPTY_SLOT(obj) OBJECT_CHECK(EmptySlot, (obj), TYPE_EMPTY_SLOT)
typedef struct EmptySlot {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint64_t size;
} EmptySlot;
@ -55,9 +59,9 @@ void empty_slot_init(hwaddr addr, uint64_t slot_size)
SysBusDevice *s;
EmptySlot *e;
dev = qdev_create(NULL, "empty_slot");
dev = qdev_create(NULL, TYPE_EMPTY_SLOT);
s = SYS_BUS_DEVICE(dev);
e = FROM_SYSBUS(EmptySlot, s);
e = EMPTY_SLOT(dev);
e->size = slot_size;
qdev_init_nofail(dev);
@ -68,7 +72,7 @@ void empty_slot_init(hwaddr addr, uint64_t slot_size)
static int empty_slot_init1(SysBusDevice *dev)
{
EmptySlot *s = FROM_SYSBUS(EmptySlot, dev);
EmptySlot *s = EMPTY_SLOT(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s,
"empty-slot", s->size);
@ -84,7 +88,7 @@ static void empty_slot_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo empty_slot_info = {
.name = "empty_slot",
.name = TYPE_EMPTY_SLOT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(EmptySlot),
.class_init = empty_slot_class_init,

15
hw/cpu/a15mpcore.c
View File

@ -23,8 +23,15 @@
/* A15MP private memory region. */
#define TYPE_A15MPCORE_PRIV "a15mpcore_priv"
#define A15MPCORE_PRIV(obj) \
OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
typedef struct A15MPPrivState {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t num_cpu;
uint32_t num_irq;
MemoryRegion container;
@ -39,7 +46,7 @@ static void a15mp_priv_set_irq(void *opaque, int irq, int level)
static int a15mp_priv_init(SysBusDevice *dev)
{
A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);
A15MPPrivState *s = A15MPCORE_PRIV(dev);
SysBusDevice *busdev;
const char *gictype = "arm_gic";
@ -58,7 +65,7 @@ static int a15mp_priv_init(SysBusDevice *dev)
sysbus_pass_irq(dev, busdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, a15mp_priv_set_irq, s->num_irq - 32);
qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s->num_irq - 32);
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x0000-0x0fff -- reserved
@ -101,7 +108,7 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo a15mp_priv_info = {
.name = "a15mpcore_priv",
.name = TYPE_A15MPCORE_PRIV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A15MPPrivState),
.class_init = a15mp_priv_class_init,

15
hw/cpu/a9mpcore.c
View File

@ -10,8 +10,15 @@
#include "hw/sysbus.h"
#define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
#define A9MPCORE_PRIV(obj) \
OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
typedef struct A9MPPrivState {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t num_cpu;
MemoryRegion container;
DeviceState *mptimer;
@ -29,7 +36,7 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int level)
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev);
A9MPPrivState *s = A9MPCORE_PRIV(dev);
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
int i;
@ -43,7 +50,7 @@ static int a9mp_priv_init(SysBusDevice *dev)
sysbus_pass_irq(dev, gicbusdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32);
qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s->num_irq - 32);
s->scu = qdev_create(NULL, "a9-scu");
qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu);
@ -124,7 +131,7 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo a9mp_priv_info = {
.name = "a9mpcore_priv",
.name = TYPE_A9MPCORE_PRIV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A9MPPrivState),
.class_init = a9mp_priv_class_init,

42
hw/cpu/arm11mpcore.c
View File

@ -12,8 +12,13 @@
/* MPCore private memory region. */
#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
#define ARM11MPCORE_PRIV(obj) \
OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
typedef struct ARM11MPCorePriveState {
SysBusDevice busdev;
SysBusDevice parent_obj;
uint32_t scu_control;
int iomemtype;
uint32_t old_timer_status[8];
@ -125,9 +130,10 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
}
}
static int mpcore_priv_init(SysBusDevice *dev)
static int mpcore_priv_init(SysBusDevice *sbd)
{
ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev);
DeviceState *dev = DEVICE(sbd);
ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
s->gic = qdev_create(NULL, "arm_gic");
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
@ -137,10 +143,10 @@ static int mpcore_priv_init(SysBusDevice *dev)
qdev_init_nofail(s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic));
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(s->gic));
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32);
qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
s->mptimer = qdev_create(NULL, "arm_mptimer");
qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
@ -151,15 +157,20 @@ static int mpcore_priv_init(SysBusDevice *dev)
qdev_init_nofail(s->wdtimer);
mpcore_priv_map_setup(s);
sysbus_init_mmio(dev, &s->container);
sysbus_init_mmio(sbd, &s->container);
return 0;
}
#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
#define REALVIEW_MPCORE_RIRQ(obj) \
OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
controllers. The output of these, plus some of the raw input lines
are fed into a single SMP-aware interrupt controller on the CPU. */
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
SysBusDevice *priv;
qemu_irq cpuic[32];
qemu_irq rvic[4][64];
@ -190,19 +201,20 @@ static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
}
}
static int realview_mpcore_init(SysBusDevice *dev)
static int realview_mpcore_init(SysBusDevice *sbd)
{
mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
DeviceState *dev = DEVICE(sbd);
mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
DeviceState *gic;
DeviceState *priv;
int n;
int i;
priv = qdev_create(NULL, "arm11mpcore_priv");
priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
qdev_init_nofail(priv);
s->priv = SYS_BUS_DEVICE(priv);
sysbus_pass_irq(dev, s->priv);
sysbus_pass_irq(sbd, s->priv);
for (i = 0; i < 32; i++) {
s->cpuic[i] = qdev_get_gpio_in(priv, i);
}
@ -214,8 +226,8 @@ static int realview_mpcore_init(SysBusDevice *dev)
s->rvic[n][i] = qdev_get_gpio_in(gic, i);
}
}
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0));
return 0;
}
@ -234,7 +246,7 @@ static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mpcore_rirq_info = {
.name = "realview_mpcore",
.name = TYPE_REALVIEW_MPCORE_RIRQ,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mpcore_rirq_state),
.class_init = mpcore_rirq_class_init,
@ -264,7 +276,7 @@ static void mpcore_priv_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mpcore_priv_info = {
.name = "arm11mpcore_priv",
.name = TYPE_ARM11MPCORE_PRIV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARM11MPCorePriveState),
.class_init = mpcore_priv_class_init,

18
hw/display/exynos4210_fimd.c
View File

@ -292,8 +292,13 @@ struct Exynos4210fimdWindow {
hwaddr fb_len; /* Framebuffer length */
};
#define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
#define EXYNOS4210_FIMD(obj) \
OBJECT_CHECK(Exynos4210fimdState, (obj), TYPE_EXYNOS4210_FIMD)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
QemuConsole *console;
qemu_irq irq[3];
@ -1108,6 +1113,7 @@ static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
* VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
Exynos4210fimdWindow *w = &s->window[win];
hwaddr fb_start_addr, fb_mapped_len;
@ -1131,8 +1137,8 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
* does not support hot-unplug.
*/
memory_region_unref(w->mem_section.mr);
w->mem_section = memory_region_find(sysbus_address_space(&s->busdev),
fb_start_addr, w->fb_len);
w->mem_section = memory_region_find(sysbus_address_space(sbd),
fb_start_addr, w->fb_len);
assert(w->mem_section.mr);
assert(w->mem_section.offset_within_address_space == fb_start_addr);
DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
@ -1328,7 +1334,7 @@ static void exynos4210_fimd_update(void *opaque)
static void exynos4210_fimd_reset(DeviceState *d)
{
Exynos4210fimdState *s = DO_UPCAST(Exynos4210fimdState, busdev.qdev, d);
Exynos4210fimdState *s = EXYNOS4210_FIMD(d);
unsigned w;
DPRINT_TRACE("Display controller reset\n");
@ -1900,7 +1906,7 @@ static const GraphicHwOps exynos4210_fimd_ops = {
static int exynos4210_fimd_init(SysBusDevice *dev)
{
Exynos4210fimdState *s = FROM_SYSBUS(Exynos4210fimdState, dev);
Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
s->ifb = NULL;
@ -1927,7 +1933,7 @@ static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo exynos4210_fimd_info = {
.name = "exynos4210.fimd",
.name = TYPE_EXYNOS4210_FIMD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210fimdState),
.class_init = exynos4210_fimd_class_init,

25
hw/display/g364fb.c
View File

@ -493,26 +493,33 @@ static void g364fb_init(DeviceState *dev, G364State *s)
memory_region_set_coalescing(&s->mem_vram);
}
#define TYPE_G364 "sysbus-g364"
#define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
G364State g364;
} G364SysBusState;
static int g364fb_sysbus_init(SysBusDevice *dev)
static int g364fb_sysbus_init(SysBusDevice *sbd)
{
G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
DeviceState *dev = DEVICE(sbd);
G364SysBusState *sbs = G364(dev);
G364State *s = &sbs->g364;
g364fb_init(&dev->qdev, s);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(dev, &s->mem_ctrl);
sysbus_init_mmio(dev, &s->mem_vram);
g364fb_init(dev, s);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_mmio(sbd, &s->mem_ctrl);
sysbus_init_mmio(sbd, &s->mem_vram);
return 0;
}
static void g364fb_sysbus_reset(DeviceState *d)
{
G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
G364SysBusState *s = G364(d);
g364fb_reset(&s->g364);
}
@ -536,7 +543,7 @@ static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo g364fb_sysbus_info = {
.name = "sysbus-g364",
.name = TYPE_G364,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(G364SysBusState),
.class_init = g364fb_sysbus_class_init,

12
hw/display/jazz_led.c
View File

@ -32,8 +32,12 @@ typedef enum {
REDRAW_NONE = 0, REDRAW_SEGMENTS = 1, REDRAW_BACKGROUND = 2,
} screen_state_t;
#define TYPE_JAZZ_LED "jazz-led"
#define JAZZ_LED(obj) OBJECT_CHECK(LedState, (obj), TYPE_JAZZ_LED)
typedef struct LedState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint8_t segments;
QemuConsole *con;
@ -262,7 +266,7 @@ static const GraphicHwOps jazz_led_ops = {
static int jazz_led_init(SysBusDevice *dev)
{
LedState *s = FROM_SYSBUS(LedState, dev);
LedState *s = JAZZ_LED(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &led_ops, s, "led", 1);
sysbus_init_mmio(dev, &s->iomem);
@ -274,7 +278,7 @@ static int jazz_led_init(SysBusDevice *dev)
static void jazz_led_reset(DeviceState *d)
{
LedState *s = DO_UPCAST(LedState, busdev.qdev, d);
LedState *s = JAZZ_LED(d);
s->segments = 0;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
@ -293,7 +297,7 @@ static void jazz_led_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo jazz_led_info = {
.name = "jazz-led",
.name = TYPE_JAZZ_LED,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LedState),
.class_init = jazz_led_class_init,

13
hw/display/milkymist-tmu2.c
View File

@ -75,8 +75,13 @@ struct vertex {
int y;
} QEMU_PACKED;
#define TYPE_MILKYMIST_TMU2 "milkymist-tmu2"
#define MILKYMIST_TMU2(obj) \
OBJECT_CHECK(MilkymistTMU2State, (obj), TYPE_MILKYMIST_TMU2)
struct MilkymistTMU2State {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion regs_region;
CharDriverState *chr;
qemu_irq irq;
@ -429,7 +434,7 @@ static const MemoryRegionOps tmu2_mmio_ops = {
static void milkymist_tmu2_reset(DeviceState *d)
{
MilkymistTMU2State *s = container_of(d, MilkymistTMU2State, busdev.qdev);
MilkymistTMU2State *s = MILKYMIST_TMU2(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -439,7 +444,7 @@ static void milkymist_tmu2_reset(DeviceState *d)
static int milkymist_tmu2_init(SysBusDevice *dev)
{
MilkymistTMU2State *s = FROM_SYSBUS(typeof(*s), dev);
MilkymistTMU2State *s = MILKYMIST_TMU2(dev);
if (tmu2_glx_init(s)) {
return 1;
@ -476,7 +481,7 @@ static void milkymist_tmu2_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_tmu2_info = {
.name = "milkymist-tmu2",
.name = TYPE_MILKYMIST_TMU2,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistTMU2State),
.class_init = milkymist_tmu2_class_init,

17
hw/display/milkymist-vgafb.c
View File

@ -63,8 +63,13 @@ enum {
CTRL_RESET = (1<<0),
};
#define TYPE_MILKYMIST_VGAFB "milkymist-vgafb"
#define MILKYMIST_VGAFB(obj) \
OBJECT_CHECK(MilkymistVgafbState, (obj), TYPE_MILKYMIST_VGAFB)
struct MilkymistVgafbState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion regs_region;
QemuConsole *con;
@ -84,6 +89,7 @@ static int vgafb_enabled(MilkymistVgafbState *s)
static void vgafb_update_display(void *opaque)
{
MilkymistVgafbState *s = opaque;
SysBusDevice *sbd;
DisplaySurface *surface = qemu_console_surface(s->con);
int first = 0;
int last = 0;
@ -93,6 +99,7 @@ static void vgafb_update_display(void *opaque)
return;
}
sbd = SYS_BUS_DEVICE(s);
int dest_width = s->regs[R_HRES];
switch (surface_bits_per_pixel(surface)) {
@ -122,7 +129,7 @@ static void vgafb_update_display(void *opaque)
break;
}
framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
framebuffer_update_display(surface, sysbus_address_space(sbd),
s->regs[R_BASEADDRESS] + s->fb_offset,
s->regs[R_HRES],
s->regs[R_VRES],
@ -256,7 +263,7 @@ static const MemoryRegionOps vgafb_mmio_ops = {
static void milkymist_vgafb_reset(DeviceState *d)
{
MilkymistVgafbState *s = container_of(d, MilkymistVgafbState, busdev.qdev);
MilkymistVgafbState *s = MILKYMIST_VGAFB(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -277,7 +284,7 @@ static const GraphicHwOps vgafb_ops = {
static int milkymist_vgafb_init(SysBusDevice *dev)
{
MilkymistVgafbState *s = FROM_SYSBUS(typeof(*s), dev);
MilkymistVgafbState *s = MILKYMIST_VGAFB(dev);
memory_region_init_io(&s->regs_region, OBJECT(s), &vgafb_mmio_ops, s,
"milkymist-vgafb", R_MAX * 4);
@ -324,7 +331,7 @@ static void milkymist_vgafb_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_vgafb_info = {
.name = "milkymist-vgafb",
.name = TYPE_MILKYMIST_VGAFB,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistVgafbState),
.class_init = milkymist_vgafb_class_init,

139
hw/display/pl110.c
View File

@ -39,8 +39,12 @@ enum pl110_version
PL111
};
typedef struct {
SysBusDevice busdev;
#define TYPE_PL110 "pl110"
#define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
typedef struct PL110State {
SysBusDevice parent_obj;
MemoryRegion iomem;
QemuConsole *con;
@ -59,7 +63,7 @@ typedef struct {
uint32_t palette[256];
uint32_t raw_palette[128];
qemu_irq irq;
} pl110_state;
} PL110State;
static int vmstate_pl110_post_load(void *opaque, int version_id);
@ -69,20 +73,20 @@ static const VMStateDescription vmstate_pl110 = {
.minimum_version_id = 1,
.post_load = vmstate_pl110_post_load,
.fields = (VMStateField[]) {
VMSTATE_INT32(version, pl110_state),
VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
VMSTATE_UINT32(cr, pl110_state),
VMSTATE_UINT32(upbase, pl110_state),
VMSTATE_UINT32(lpbase, pl110_state),
VMSTATE_UINT32(int_status, pl110_state),
VMSTATE_UINT32(int_mask, pl110_state),
VMSTATE_INT32(cols, pl110_state),
VMSTATE_INT32(rows, pl110_state),
VMSTATE_UINT32(bpp, pl110_state),
VMSTATE_INT32(invalidate, pl110_state),
VMSTATE_UINT32_ARRAY(palette, pl110_state, 256),
VMSTATE_UINT32_ARRAY(raw_palette, pl110_state, 128),
VMSTATE_UINT32_V(mux_ctrl, pl110_state, 2),
VMSTATE_INT32(version, PL110State),
VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
VMSTATE_UINT32(cr, PL110State),
VMSTATE_UINT32(upbase, PL110State),
VMSTATE_UINT32(lpbase, PL110State),
VMSTATE_UINT32(int_status, PL110State),
VMSTATE_UINT32(int_mask, PL110State),
VMSTATE_INT32(cols, PL110State),
VMSTATE_INT32(rows, PL110State),
VMSTATE_UINT32(bpp, PL110State),
VMSTATE_INT32(invalidate, PL110State),
VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
VMSTATE_END_OF_LIST()
}
};
@ -121,14 +125,15 @@ static const unsigned char *idregs[] = {
#define BITS 32
#include "pl110_template.h"
static int pl110_enabled(pl110_state *s)
static int pl110_enabled(PL110State *s)
{
return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
}
static void pl110_update_display(void *opaque)
{
pl110_state *s = (pl110_state *)opaque;
PL110State *s = (PL110State *)opaque;
SysBusDevice *sbd;
DisplaySurface *surface = qemu_console_surface(s->con);
drawfn* fntable;
drawfn fn;
@ -138,8 +143,11 @@ static void pl110_update_display(void *opaque)
int first;
int last;
if (!pl110_enabled(s))
if (!pl110_enabled(s)) {
return;
}
sbd = SYS_BUS_DEVICE(s);
switch (surface_bits_per_pixel(surface)) {
case 0:
@ -232,7 +240,7 @@ static void pl110_update_display(void *opaque)
}
dest_width *= s->cols;
first = 0;
framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
framebuffer_update_display(surface, sysbus_address_space(sbd),
s->upbase, s->cols, s->rows,
src_width, dest_width, 0,
s->invalidate,
@ -246,14 +254,14 @@ static void pl110_update_display(void *opaque)
static void pl110_invalidate_display(void * opaque)
{
pl110_state *s = (pl110_state *)opaque;
PL110State *s = (PL110State *)opaque;
s->invalidate = 1;
if (pl110_enabled(s)) {
qemu_console_resize(s->con, s->cols, s->rows);
}
}
static void pl110_update_palette(pl110_state *s, int n)
static void pl110_update_palette(PL110State *s, int n)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int i;
@ -289,7 +297,7 @@ static void pl110_update_palette(pl110_state *s, int n)
}
}
static void pl110_resize(pl110_state *s, int width, int height)
static void pl110_resize(PL110State *s, int width, int height)
{
if (width != s->cols || height != s->rows) {
if (pl110_enabled(s)) {
@ -301,7 +309,7 @@ static void pl110_resize(pl110_state *s, int width, int height)
}
/* Update interrupts. */
static void pl110_update(pl110_state *s)
static void pl110_update(PL110State *s)
{
/* TODO: Implement interrupts. */
}
@ -309,7 +317,7 @@ static void pl110_update(pl110_state *s)
static uint64_t pl110_read(void *opaque, hwaddr offset,
unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
PL110State *s = (PL110State *)opaque;
if (offset >= 0xfe0 && offset < 0x1000) {
return idregs[s->version][(offset - 0xfe0) >> 2];
@ -359,7 +367,7 @@ static uint64_t pl110_read(void *opaque, hwaddr offset,
static void pl110_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
PL110State *s = (PL110State *)opaque;
int n;
/* For simplicity invalidate the display whenever a control register
@ -432,13 +440,13 @@ static const MemoryRegionOps pl110_ops = {
static void pl110_mux_ctrl_set(void *opaque, int line, int level)
{
pl110_state *s = (pl110_state *)opaque;
PL110State *s = (PL110State *)opaque;
s->mux_ctrl = level;
}
static int vmstate_pl110_post_load(void *opaque, int version_id)
{
pl110_state *s = opaque;
PL110State *s = opaque;
/* Make sure we redraw, and at the right size */
pl110_invalidate_display(s);
return 0;
@ -449,30 +457,38 @@ static const GraphicHwOps pl110_gfx_ops = {
.gfx_update = pl110_update_display,
};
static int pl110_init(SysBusDevice *dev)
static int pl110_initfn(SysBusDevice *sbd)
{
pl110_state *s = FROM_SYSBUS(pl110_state, dev);
DeviceState *dev = DEVICE(sbd);
PL110State *s = PL110(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
s->con = graphic_console_init(DEVICE(dev), &pl110_gfx_ops, s);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
s->con = graphic_console_init(dev, &pl110_gfx_ops, s);
return 0;
}
static int pl110_versatile_init(SysBusDevice *dev)
static void pl110_init(Object *obj)
{
pl110_state *s = FROM_SYSBUS(pl110_state, dev);
s->version = PL110_VERSATILE;
return pl110_init(dev);
PL110State *s = PL110(obj);
s->version = PL110;
}
static int pl111_init(SysBusDevice *dev)
static void pl110_versatile_init(Object *obj)
{
pl110_state *s = FROM_SYSBUS(pl110_state, dev);
PL110State *s = PL110(obj);
s->version = PL110_VERSATILE;
}
static void pl111_init(Object *obj)
{
PL110State *s = PL110(obj);
s->version = PL111;
return pl110_init(dev);
}
static void pl110_class_init(ObjectClass *klass, void *data)
@ -480,53 +496,30 @@ static void pl110_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl110_init;
k->init = pl110_initfn;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->no_user = 1;
dc->vmsd = &vmstate_pl110;
}
static const TypeInfo pl110_info = {
.name = "pl110",
.name = TYPE_PL110,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl110_state),
.instance_size = sizeof(PL110State),
.instance_init = pl110_init,
.class_init = pl110_class_init,
};
static void pl110_versatile_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl110_versatile_init;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->no_user = 1;
dc->vmsd = &vmstate_pl110;
}
static const TypeInfo pl110_versatile_info = {
.name = "pl110_versatile",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl110_state),
.class_init = pl110_versatile_class_init,
.parent = TYPE_PL110,
.instance_init = pl110_versatile_init,
};
static void pl111_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl111_init;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->no_user = 1;
dc->vmsd = &vmstate_pl110;
}
static const TypeInfo pl111_info = {
.name = "pl111",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl110_state),
.class_init = pl111_class_init,
.parent = TYPE_PL110,
.instance_init = pl111_init,
};
static void pl110_register_types(void)

12
hw/display/tcx.c
View File

@ -34,8 +34,12 @@
#define TCX_THC_NREGS_24 0x1000
#define TCX_TEC_NREGS 0x1000
#define TYPE_TCX "SUNW,tcx"
#define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX)
typedef struct TCXState {
SysBusDevice busdev;
SysBusDevice parent_obj;
QemuConsole *con;
uint8_t *vram;
uint32_t *vram24, *cplane;
@ -423,7 +427,7 @@ static const VMStateDescription vmstate_tcx = {
static void tcx_reset(DeviceState *d)
{
TCXState *s = container_of(d, TCXState, busdev.qdev);
TCXState *s = TCX(d);
/* Initialize palette */
memset(s->r, 0, 256);
@ -523,7 +527,7 @@ static const GraphicHwOps tcx24_ops = {
static int tcx_init1(SysBusDevice *dev)
{
TCXState *s = FROM_SYSBUS(TCXState, dev);
TCXState *s = TCX(dev);
ram_addr_t vram_offset = 0;
int size;
uint8_t *vram_base;
@ -609,7 +613,7 @@ static void tcx_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo tcx_info = {
.name = "SUNW,tcx",
.name = TYPE_TCX,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(TCXState),
.class_init = tcx_class_init,

93
hw/dma/pl080.c
View File

@ -35,8 +35,12 @@ typedef struct {
uint32_t conf;
} pl080_channel;
typedef struct {
SysBusDevice busdev;
#define TYPE_PL080 "pl080"
#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
typedef struct PL080State {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint8_t tc_int;
uint8_t tc_mask;
@ -51,7 +55,7 @@ typedef struct {
/* Flag to avoid recursive DMA invocations. */
int running;
qemu_irq irq;
} pl080_state;
} PL080State;
static const VMStateDescription vmstate_pl080_channel = {
.name = "pl080_channel",
@ -72,20 +76,20 @@ static const VMStateDescription vmstate_pl080 = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(tc_int, pl080_state),
VMSTATE_UINT8(tc_mask, pl080_state),
VMSTATE_UINT8(err_int, pl080_state),
VMSTATE_UINT8(err_mask, pl080_state),
VMSTATE_UINT32(conf, pl080_state),
VMSTATE_UINT32(sync, pl080_state),
VMSTATE_UINT32(req_single, pl080_state),
VMSTATE_UINT32(req_burst, pl080_state),
VMSTATE_UINT8(tc_int, pl080_state),
VMSTATE_UINT8(tc_int, pl080_state),
VMSTATE_UINT8(tc_int, pl080_state),
VMSTATE_STRUCT_ARRAY(chan, pl080_state, PL080_MAX_CHANNELS,
VMSTATE_UINT8(tc_int, PL080State),
VMSTATE_UINT8(tc_mask, PL080State),
VMSTATE_UINT8(err_int, PL080State),
VMSTATE_UINT8(err_mask, PL080State),
VMSTATE_UINT32(conf, PL080State),
VMSTATE_UINT32(sync, PL080State),
VMSTATE_UINT32(req_single, PL080State),
VMSTATE_UINT32(req_burst, PL080State),
VMSTATE_UINT8(tc_int, PL080State),
VMSTATE_UINT8(tc_int, PL080State),
VMSTATE_UINT8(tc_int, PL080State),
VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
1, vmstate_pl080_channel, pl080_channel),
VMSTATE_INT32(running, pl080_state),
VMSTATE_INT32(running, PL080State),
VMSTATE_END_OF_LIST()
}
};
@ -96,7 +100,7 @@ static const unsigned char pl080_id[] =
static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
static void pl080_update(pl080_state *s)
static void pl080_update(PL080State *s)
{
if ((s->tc_int & s->tc_mask)
|| (s->err_int & s->err_mask))
@ -105,7 +109,7 @@ static void pl080_update(pl080_state *s)
qemu_irq_lower(s->irq);
}
static void pl080_run(pl080_state *s)
static void pl080_run(PL080State *s)
{
int c;
int flow;
@ -221,7 +225,7 @@ again:
static uint64_t pl080_read(void *opaque, hwaddr offset,
unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
PL080State *s = (PL080State *)opaque;
uint32_t i;
uint32_t mask;
@ -290,7 +294,7 @@ static uint64_t pl080_read(void *opaque, hwaddr offset,
static void pl080_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
PL080State *s = (PL080State *)opaque;
int i;
if (offset >= 0x100 && offset < 0x200) {
@ -355,59 +359,44 @@ static const MemoryRegionOps pl080_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl08x_init(SysBusDevice *dev, int nchannels)
static void pl080_init(Object *obj)
{
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PL080State *s = PL080(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->nchannels = nchannels;
return 0;
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
s->nchannels = 8;
}
static int pl080_init(SysBusDevice *dev)
static void pl081_init(Object *obj)
{
return pl08x_init(dev, 8);
PL080State *s = PL080(obj);
s->nchannels = 2;
}
static int pl081_init(SysBusDevice *dev)
static void pl080_class_init(ObjectClass *oc, void *data)
{
return pl08x_init(dev, 2);
}
DeviceClass *dc = DEVICE_CLASS(oc);
static void pl080_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl080_init;
dc->no_user = 1;
dc->vmsd = &vmstate_pl080;
}
static const TypeInfo pl080_info = {
.name = "pl080",
.name = TYPE_PL080,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl080_state),
.instance_size = sizeof(PL080State),
.instance_init = pl080_init,
.class_init = pl080_class_init,
};
static void pl081_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl081_init;
dc->no_user = 1;
dc->vmsd = &vmstate_pl080;
}
static const TypeInfo pl081_info = {
.name = "pl081",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl080_state),
.class_init = pl081_class_init,
.parent = TYPE_PL080,
.instance_init = pl081_init,
};
/* The PL080 and PL081 are the same except for the number of channels

12
hw/dma/puv3_dma.c
View File

@ -18,8 +18,12 @@
#define PUV3_DMA_CH_MASK (0xff)
#define PUV3_DMA_CH(offset) ((offset) >> 8)
typedef struct {
SysBusDevice busdev;
#define TYPE_PUV3_DMA "puv3_dma"
#define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA)
typedef struct PUV3DMAState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t reg_CFG[PUV3_DMA_CH_NR];
} PUV3DMAState;
@ -73,7 +77,7 @@ static const MemoryRegionOps puv3_dma_ops = {
static int puv3_dma_init(SysBusDevice *dev)
{
PUV3DMAState *s = FROM_SYSBUS(PUV3DMAState, dev);
PUV3DMAState *s = PUV3_DMA(dev);
int i;
for (i = 0; i < PUV3_DMA_CH_NR; i++) {
@ -95,7 +99,7 @@ static void puv3_dma_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo puv3_dma_info = {
.name = "puv3_dma",
.name = TYPE_PUV3_DMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PUV3DMAState),
.class_init = puv3_dma_class_init,

20
hw/dma/pxa2xx_dma.c
View File

@ -26,8 +26,12 @@ typedef struct {
int request;
} PXA2xxDMAChannel;
#define TYPE_PXA2XX_DMA "pxa2xx-dma"
#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)
typedef struct PXA2xxDMAState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
@ -445,11 +449,11 @@ static void pxa2xx_dma_request(void *opaque, int req_num, int on)
}
}
static int pxa2xx_dma_init(SysBusDevice *dev)
static int pxa2xx_dma_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
PXA2xxDMAState *s = PXA2XX_DMA(dev);
int i;
PXA2xxDMAState *s;
s = FROM_SYSBUS(PXA2xxDMAState, dev);
if (s->channels <= 0) {
return -1;
@ -463,12 +467,12 @@ static int pxa2xx_dma_init(SysBusDevice *dev)
memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_dma_ops, s,
"pxa2xx.dma", 0x00010000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
return 0;
}
@ -560,7 +564,7 @@ static void pxa2xx_dma_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pxa2xx_dma_info = {
.name = "pxa2xx-dma",
.name = TYPE_PXA2XX_DMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PXA2xxDMAState),
.class_init = pxa2xx_dma_class_init,

23
hw/dma/sparc32_dma.c
View File

@ -60,10 +60,14 @@
/* XXX SCSI and ethernet should have different read-only bit masks */
#define DMA_CSR_RO_MASK 0xfe000007
#define TYPE_SPARC32_DMA "sparc32_dma"
#define SPARC32_DMA(obj) OBJECT_CHECK(DMAState, (obj), TYPE_SPARC32_DMA)
typedef struct DMAState DMAState;
struct DMAState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t dmaregs[DMA_REGS];
qemu_irq irq;
@ -249,7 +253,7 @@ static const MemoryRegionOps dma_mem_ops = {
static void dma_reset(DeviceState *d)
{
DMAState *s = container_of(d, DMAState, busdev.qdev);
DMAState *s = SPARC32_DMA(d);
memset(s->dmaregs, 0, DMA_SIZE);
s->dmaregs[0] = DMA_VER;
@ -266,20 +270,21 @@ static const VMStateDescription vmstate_dma = {
}
};
static int sparc32_dma_init1(SysBusDevice *dev)
static int sparc32_dma_init1(SysBusDevice *sbd)
{
DMAState *s = FROM_SYSBUS(DMAState, dev);
DeviceState *dev = DEVICE(sbd);
DMAState *s = SPARC32_DMA(dev);
int reg_size;
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"dma", reg_size);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
qdev_init_gpio_in(dev, dma_set_irq, 1);
qdev_init_gpio_out(dev, s->gpio, 2);
return 0;
}
@ -302,7 +307,7 @@ static void sparc32_dma_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sparc32_dma_info = {
.name = "sparc32_dma",
.name = TYPE_SPARC32_DMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(DMAState),
.class_init = sparc32_dma_class_init,

12
hw/dma/sun4m_iommu.c
View File

@ -126,8 +126,12 @@
#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
#define TYPE_SUN4M_IOMMU "iommu"
#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU)
typedef struct IOMMUState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t regs[IOMMU_NREGS];
hwaddr iostart;
@ -332,7 +336,7 @@ static const VMStateDescription vmstate_iommu = {
static void iommu_reset(DeviceState *d)
{
IOMMUState *s = container_of(d, IOMMUState, busdev.qdev);
IOMMUState *s = SUN4M_IOMMU(d);
memset(s->regs, 0, IOMMU_NREGS * 4);
s->iostart = 0;
@ -345,7 +349,7 @@ static void iommu_reset(DeviceState *d)
static int iommu_init1(SysBusDevice *dev)
{
IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
IOMMUState *s = SUN4M_IOMMU(dev);
sysbus_init_irq(dev, &s->irq);
@ -373,7 +377,7 @@ static void iommu_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo iommu_info = {
.name = "iommu",
.name = TYPE_SUN4M_IOMMU,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IOMMUState),
.class_init = iommu_class_init,

62
hw/gpio/omap_gpio.c
View File

@ -35,8 +35,13 @@ struct omap_gpio_s {
uint16_t pins;
};
#define TYPE_OMAP1_GPIO "omap-gpio"
#define OMAP1_GPIO(obj) \
OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
struct omap_gpif_s {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
int mpu_model;
void *clk;
@ -203,8 +208,13 @@ struct omap2_gpio_s {
uint8_t delay;
};
#define TYPE_OMAP2_GPIO "omap2-gpio"
#define OMAP2_GPIO(obj) \
OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
struct omap2_gpif_s {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
int mpu_model;
void *iclk;
@ -587,16 +597,16 @@ static const MemoryRegionOps omap2_gpio_module_ops = {
static void omap_gpif_reset(DeviceState *dev)
{
struct omap_gpif_s *s = FROM_SYSBUS(struct omap_gpif_s,
SYS_BUS_DEVICE(dev));
struct omap_gpif_s *s = OMAP1_GPIO(dev);
omap_gpio_reset(&s->omap1);
}
static void omap2_gpif_reset(DeviceState *dev)
{
struct omap2_gpif_s *s = OMAP2_GPIO(dev);
int i;
struct omap2_gpif_s *s = FROM_SYSBUS(struct omap2_gpif_s,
SYS_BUS_DEVICE(dev));
for (i = 0; i < s->modulecount; i++) {
omap2_gpio_module_reset(&s->modules[i]);
}
@ -648,7 +658,7 @@ static void omap2_gpif_top_write(void *opaque, hwaddr addr,
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
if (value & (1 << 1)) /* SOFTRESET */
omap2_gpif_reset(&s->busdev.qdev);
omap2_gpif_reset(DEVICE(s));
s->autoidle = value & 1;
break;
@ -668,25 +678,29 @@ static const MemoryRegionOps omap2_gpif_top_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int omap_gpio_init(SysBusDevice *dev)
static int omap_gpio_init(SysBusDevice *sbd)
{
struct omap_gpif_s *s = FROM_SYSBUS(struct omap_gpif_s, dev);
DeviceState *dev = DEVICE(sbd);
struct omap_gpif_s *s = OMAP1_GPIO(dev);
if (!s->clk) {
hw_error("omap-gpio: clk not connected\n");
}
qdev_init_gpio_in(&dev->qdev, omap_gpio_set, 16);
qdev_init_gpio_out(&dev->qdev, s->omap1.handler, 16);
sysbus_init_irq(dev, &s->omap1.irq);
qdev_init_gpio_in(dev, omap_gpio_set, 16);
qdev_init_gpio_out(dev, s->omap1.handler, 16);
sysbus_init_irq(sbd, &s->omap1.irq);
memory_region_init_io(&s->iomem, OBJECT(s), &omap_gpio_ops, &s->omap1,
"omap.gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
static int omap2_gpio_init(SysBusDevice *dev)
static int omap2_gpio_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
struct omap2_gpif_s *s = OMAP2_GPIO(dev);
int i;
struct omap2_gpif_s *s = FROM_SYSBUS(struct omap2_gpif_s, dev);
if (!s->iclk) {
hw_error("omap2-gpio: iclk not connected\n");
}
@ -694,14 +708,14 @@ static int omap2_gpio_init(SysBusDevice *dev)
s->modulecount = (s->mpu_model < omap2430) ? 4 : 5;
memory_region_init_io(&s->iomem, OBJECT(s), &omap2_gpif_top_ops, s,
"omap2.gpio", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
} else {
s->modulecount = 6;
}
s->modules = g_malloc0(s->modulecount * sizeof(struct omap2_gpio_s));
s->handler = g_malloc0(s->modulecount * 32 * sizeof(qemu_irq));
qdev_init_gpio_in(&dev->qdev, omap2_gpio_set, s->modulecount * 32);
qdev_init_gpio_out(&dev->qdev, s->handler, s->modulecount * 32);
qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
for (i = 0; i < s->modulecount; i++) {
struct omap2_gpio_s *m = &s->modules[i];
if (!s->fclk[i]) {
@ -709,12 +723,12 @@ static int omap2_gpio_init(SysBusDevice *dev)
}
m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
m->handler = &s->handler[i * 32];
sysbus_init_irq(dev, &m->irq[0]); /* mpu irq */
sysbus_init_irq(dev, &m->irq[1]); /* dsp irq */
sysbus_init_irq(dev, &m->wkup);
sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
sysbus_init_irq(sbd, &m->wkup);
memory_region_init_io(&m->iomem, OBJECT(s), &omap2_gpio_module_ops, m,
"omap.gpio-module", 0x1000);
sysbus_init_mmio(dev, &m->iomem);
sysbus_init_mmio(sbd, &m->iomem);
}
return 0;
}
@ -748,7 +762,7 @@ static void omap_gpio_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo omap_gpio_info = {
.name = "omap-gpio",
.name = TYPE_OMAP1_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap_gpif_s),
.class_init = omap_gpio_class_init,
@ -777,7 +791,7 @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo omap2_gpio_info = {
.name = "omap2-gpio",
.name = TYPE_OMAP2_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap2_gpif_s),
.class_init = omap2_gpio_class_init,

110
hw/gpio/pl061.c
View File

@ -28,8 +28,12 @@ static const uint8_t pl061_id[12] =
static const uint8_t pl061_id_luminary[12] =
{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
typedef struct {
SysBusDevice busdev;
#define TYPE_PL061 "pl061"
#define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061)
typedef struct PL061State {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t locked;
uint32_t data;
@ -55,39 +59,39 @@ typedef struct {
qemu_irq irq;
qemu_irq out[8];
const unsigned char *id;
} pl061_state;
} PL061State;
static const VMStateDescription vmstate_pl061 = {
.name = "pl061",
.version_id = 2,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(locked, pl061_state),
VMSTATE_UINT32(data, pl061_state),
VMSTATE_UINT32(old_data, pl061_state),
VMSTATE_UINT32(dir, pl061_state),
VMSTATE_UINT32(isense, pl061_state),
VMSTATE_UINT32(ibe, pl061_state),
VMSTATE_UINT32(iev, pl061_state),
VMSTATE_UINT32(im, pl061_state),
VMSTATE_UINT32(istate, pl061_state),
VMSTATE_UINT32(afsel, pl061_state),
VMSTATE_UINT32(dr2r, pl061_state),
VMSTATE_UINT32(dr4r, pl061_state),
VMSTATE_UINT32(dr8r, pl061_state),
VMSTATE_UINT32(odr, pl061_state),
VMSTATE_UINT32(pur, pl061_state),
VMSTATE_UINT32(pdr, pl061_state),
VMSTATE_UINT32(slr, pl061_state),
VMSTATE_UINT32(den, pl061_state),
VMSTATE_UINT32(cr, pl061_state),
VMSTATE_UINT32(float_high, pl061_state),
VMSTATE_UINT32_V(amsel, pl061_state, 2),
VMSTATE_UINT32(locked, PL061State),
VMSTATE_UINT32(data, PL061State),
VMSTATE_UINT32(old_data, PL061State),
VMSTATE_UINT32(dir, PL061State),
VMSTATE_UINT32(isense, PL061State),
VMSTATE_UINT32(ibe, PL061State),
VMSTATE_UINT32(iev, PL061State),
VMSTATE_UINT32(im, PL061State),
VMSTATE_UINT32(istate, PL061State),
VMSTATE_UINT32(afsel, PL061State),
VMSTATE_UINT32(dr2r, PL061State),
VMSTATE_UINT32(dr4r, PL061State),
VMSTATE_UINT32(dr8r, PL061State),
VMSTATE_UINT32(odr, PL061State),
VMSTATE_UINT32(pur, PL061State),
VMSTATE_UINT32(pdr, PL061State),
VMSTATE_UINT32(slr, PL061State),
VMSTATE_UINT32(den, PL061State),
VMSTATE_UINT32(cr, PL061State),
VMSTATE_UINT32(float_high, PL061State),
VMSTATE_UINT32_V(amsel, PL061State, 2),
VMSTATE_END_OF_LIST()
}
};
static void pl061_update(pl061_state *s)
static void pl061_update(PL061State *s)
{
uint8_t changed;
uint8_t mask;
@ -116,7 +120,7 @@ static void pl061_update(pl061_state *s)
static uint64_t pl061_read(void *opaque, hwaddr offset,
unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
PL061State *s = (PL061State *)opaque;
if (offset >= 0xfd0 && offset < 0x1000) {
return s->id[(offset - 0xfd0) >> 2];
@ -173,7 +177,7 @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
static void pl061_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
PL061State *s = (PL061State *)opaque;
uint8_t mask;
if (offset < 0x400) {
@ -246,7 +250,7 @@ static void pl061_write(void *opaque, hwaddr offset,
pl061_update(s);
}
static void pl061_reset(pl061_state *s)
static void pl061_reset(PL061State *s)
{
s->locked = 1;
s->cr = 0xff;
@ -254,7 +258,7 @@ static void pl061_reset(pl061_state *s)
static void pl061_set_irq(void * opaque, int irq, int level)
{
pl061_state *s = (pl061_state *)opaque;
PL061State *s = (PL061State *)opaque;
uint8_t mask;
mask = 1 << irq;
@ -272,27 +276,32 @@ static const MemoryRegionOps pl061_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl061_init(SysBusDevice *dev, const unsigned char *id)
static int pl061_initfn(SysBusDevice *sbd)
{
pl061_state *s = FROM_SYSBUS(pl061_state, dev);
s->id = id;
DeviceState *dev = DEVICE(sbd);
PL061State *s = PL061(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &pl061_ops, s, "pl061", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
qdev_init_gpio_out(&dev->qdev, s->out, 8);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, pl061_set_irq, 8);
qdev_init_gpio_out(dev, s->out, 8);
pl061_reset(s);
return 0;
}
static int pl061_init_luminary(SysBusDevice *dev)
static void pl061_luminary_init(Object *obj)
{
return pl061_init(dev, pl061_id_luminary);
PL061State *s = PL061(obj);
s->id = pl061_id_luminary;
}
static int pl061_init_arm(SysBusDevice *dev)
static void pl061_init(Object *obj)
{
return pl061_init(dev, pl061_id);
PL061State *s = PL061(obj);
s->id = pl061_id;
}
static void pl061_class_init(ObjectClass *klass, void *data)
@ -300,31 +309,22 @@ static void pl061_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl061_init_arm;
k->init = pl061_initfn;
dc->vmsd = &vmstate_pl061;
}
static const TypeInfo pl061_info = {
.name = "pl061",
.name = TYPE_PL061,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl061_state),
.instance_size = sizeof(PL061State),
.instance_init = pl061_init,
.class_init = pl061_class_init,
};
static void pl061_luminary_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl061_init_luminary;
dc->vmsd = &vmstate_pl061;
}
static const TypeInfo pl061_luminary_info = {
.name = "pl061_luminary",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl061_state),
.class_init = pl061_luminary_class_init,
.parent = TYPE_PL061,
.instance_init = pl061_luminary_init,
};
static void pl061_register_types(void)

12
hw/gpio/puv3_gpio.c
View File

@ -14,8 +14,12 @@
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
typedef struct {
SysBusDevice busdev;
#define TYPE_PUV3_GPIO "puv3_gpio"
#define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
typedef struct PUV3GPIOState {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq[9];
@ -96,7 +100,7 @@ static const MemoryRegionOps puv3_gpio_ops = {
static int puv3_gpio_init(SysBusDevice *dev)
{
PUV3GPIOState *s = FROM_SYSBUS(PUV3GPIOState, dev);
PUV3GPIOState *s = PUV3_GPIO(dev);
s->reg_GPLR = 0;
s->reg_GPDR = 0;
@ -127,7 +131,7 @@ static void puv3_gpio_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo puv3_gpio_info = {
.name = "puv3_gpio",
.name = TYPE_PUV3_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PUV3GPIOState),
.class_init = puv3_gpio_class_init,

19
hw/gpio/zaurus.c
View File

@ -24,9 +24,13 @@
/* SCOOP devices */
#define TYPE_SCOOP "scoop"
#define SCOOP(obj) OBJECT_CHECK(ScoopInfo, (obj), TYPE_SCOOP)
typedef struct ScoopInfo ScoopInfo;
struct ScoopInfo {
SysBusDevice busdev;
SysBusDevice parent_obj;
qemu_irq handler[16];
MemoryRegion iomem;
uint16_t status;
@ -162,16 +166,17 @@ static void scoop_gpio_set(void *opaque, int line, int level)
s->gpio_level &= ~(1 << line);
}
static int scoop_init(SysBusDevice *dev)
static int scoop_init(SysBusDevice *sbd)
{
ScoopInfo *s = FROM_SYSBUS(ScoopInfo, dev);
DeviceState *dev = DEVICE(sbd);
ScoopInfo *s = SCOOP(dev);
s->status = 0x02;
qdev_init_gpio_out(&s->busdev.qdev, s->handler, 16);
qdev_init_gpio_in(&s->busdev.qdev, scoop_gpio_set, 16);
qdev_init_gpio_out(dev, s->handler, 16);
qdev_init_gpio_in(dev, scoop_gpio_set, 16);
memory_region_init_io(&s->iomem, OBJECT(s), &scoop_ops, s, "scoop", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -237,7 +242,7 @@ static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo scoop_sysbus_info = {
.name = "scoop",
.name = TYPE_SCOOP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ScoopInfo),
.class_init = scoop_sysbus_class_init,

24
hw/i2c/bitbang_i2c.c
View File

@ -185,8 +185,13 @@ bitbang_i2c_interface *bitbang_i2c_init(i2c_bus *bus)
}
/* GPIO interface. */
typedef struct {
SysBusDevice busdev;
#define TYPE_GPIO_I2C "gpio_i2c"
#define GPIO_I2C(obj) OBJECT_CHECK(GPIOI2CState, (obj), TYPE_GPIO_I2C)
typedef struct GPIOI2CState {
SysBusDevice parent_obj;
MemoryRegion dummy_iomem;
bitbang_i2c_interface *bitbang;
int last_level;
@ -204,19 +209,20 @@ static void bitbang_i2c_gpio_set(void *opaque, int irq, int level)
}
}
static int gpio_i2c_init(SysBusDevice *dev)
static int gpio_i2c_init(SysBusDevice *sbd)
{
GPIOI2CState *s = FROM_SYSBUS(GPIOI2CState, dev);
DeviceState *dev = DEVICE(sbd);
GPIOI2CState *s = GPIO_I2C(dev);
i2c_bus *bus;
memory_region_init(&s->dummy_iomem, OBJECT(s), "gpio_i2c", 0);
sysbus_init_mmio(dev, &s->dummy_iomem);
sysbus_init_mmio(sbd, &s->dummy_iomem);
bus = i2c_init_bus(&dev->qdev, "i2c");
bus = i2c_init_bus(dev, "i2c");
s->bitbang = bitbang_i2c_init(bus);
qdev_init_gpio_in(&dev->qdev, bitbang_i2c_gpio_set, 2);
qdev_init_gpio_out(&dev->qdev, &s->out, 1);
qdev_init_gpio_in(dev, bitbang_i2c_gpio_set, 2);
qdev_init_gpio_out(dev, &s->out, 1);
return 0;
}
@ -232,7 +238,7 @@ static void gpio_i2c_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo gpio_i2c_info = {
.name = "gpio_i2c",
.name = TYPE_GPIO_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(GPIOI2CState),
.class_init = gpio_i2c_class_init,

12
hw/i2c/exynos4210_i2c.c
View File

@ -80,7 +80,8 @@ static const char *exynos4_i2c_get_regname(unsigned offset)
#endif
typedef struct Exynos4210I2CState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
i2c_bus *bus;
qemu_irq irq;
@ -297,15 +298,16 @@ static void exynos4210_i2c_reset(DeviceState *d)
s->scl_free = true;
}
static int exynos4210_i2c_realize(SysBusDevice *dev)
static int exynos4210_i2c_realize(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
Exynos4210I2CState *s = EXYNOS4_I2C(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_i2c_ops, s,
TYPE_EXYNOS4_I2C, EXYNOS4_I2C_MEM_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->bus = i2c_init_bus(&dev->qdev, "i2c");
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
s->bus = i2c_init_bus(dev, "i2c");
return 0;
}

38
hw/i2c/omap_i2c.c
View File

@ -21,9 +21,12 @@
#include "hw/arm/omap.h"
#include "hw/sysbus.h"
#define TYPE_OMAP_I2C "omap_i2c"
#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
typedef struct OMAPI2CState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
qemu_irq drq[2];
@ -130,8 +133,8 @@ static void omap_i2c_fifo_run(OMAPI2CState *s)
static void omap_i2c_reset(DeviceState *dev)
{
OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState,
SYS_BUS_DEVICE(dev));
OMAPI2CState *s = OMAP_I2C(dev);
s->mask = 0;
s->stat = 0;
s->dma = 0;
@ -316,15 +319,17 @@ static void omap_i2c_write(void *opaque, hwaddr addr,
return;
}
if (value & 2)
omap_i2c_reset(&s->busdev.qdev);
if (value & 2) {
omap_i2c_reset(DEVICE(s));
}
break;
case 0x24: /* I2C_CON */
s->control = value & 0xcf87;
if (~value & (1 << 15)) { /* I2C_EN */
if (s->revision < OMAP2_INTR_REV)
omap_i2c_reset(&s->busdev.qdev);
if (s->revision < OMAP2_INTR_REV) {
omap_i2c_reset(DEVICE(s));
}
break;
}
if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
@ -434,9 +439,10 @@ static const MemoryRegionOps omap_i2c_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int omap_i2c_init(SysBusDevice *dev)
static int omap_i2c_init(SysBusDevice *sbd)
{
OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, dev);
DeviceState *dev = DEVICE(sbd);
OMAPI2CState *s = OMAP_I2C(dev);
if (!s->fclk) {
hw_error("omap_i2c: fclk not connected\n");
@ -445,13 +451,13 @@ static int omap_i2c_init(SysBusDevice *dev)
/* Note that OMAP1 doesn't have a separate interface clock */
hw_error("omap_i2c: iclk not connected\n");
}
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->drq[0]);
sysbus_init_irq(dev, &s->drq[1]);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->drq[0]);
sysbus_init_irq(sbd, &s->drq[1]);
memory_region_init_io(&s->iomem, OBJECT(s), &omap_i2c_ops, s, "omap.i2c",
(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
sysbus_init_mmio(dev, &s->iomem);
s->bus = i2c_init_bus(&dev->qdev, NULL);
sysbus_init_mmio(sbd, &s->iomem);
s->bus = i2c_init_bus(dev, NULL);
return 0;
}
@ -472,7 +478,7 @@ static void omap_i2c_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo omap_i2c_info = {
.name = "omap_i2c",
.name = TYPE_OMAP_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OMAPI2CState),
.class_init = omap_i2c_class_init,
@ -485,7 +491,7 @@ static void omap_i2c_register_types(void)
i2c_bus *omap_i2c_bus(DeviceState *omap_i2c)
{
OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, SYS_BUS_DEVICE(omap_i2c));
OMAPI2CState *s = OMAP_I2C(omap_i2c);
return s->bus;
}

20
hw/i2c/versatile_i2c.c
View File

@ -24,8 +24,13 @@
#include "hw/sysbus.h"
#include "bitbang_i2c.h"
typedef struct {
SysBusDevice busdev;
#define TYPE_VERSATILE_I2C "versatile_i2c"
#define VERSATILE_I2C(obj) \
OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
typedef struct VersatileI2CState {
SysBusDevice parent_obj;
MemoryRegion iomem;
bitbang_i2c_interface *bitbang;
int out;
@ -72,16 +77,17 @@ static const MemoryRegionOps versatile_i2c_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int versatile_i2c_init(SysBusDevice *dev)
static int versatile_i2c_init(SysBusDevice *sbd)
{
VersatileI2CState *s = FROM_SYSBUS(VersatileI2CState, dev);
DeviceState *dev = DEVICE(sbd);
VersatileI2CState *s = VERSATILE_I2C(dev);
i2c_bus *bus;
bus = i2c_init_bus(&dev->qdev, "i2c");
bus = i2c_init_bus(dev, "i2c");
s->bitbang = bitbang_i2c_init(bus);
memory_region_init_io(&s->iomem, OBJECT(s), &versatile_i2c_ops, s,
"versatile_i2c", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -93,7 +99,7 @@ static void versatile_i2c_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo versatile_i2c_info = {
.name = "versatile_i2c",
.name = TYPE_VERSATILE_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(VersatileI2CState),
.class_init = versatile_i2c_class_init,

4
hw/i386/kvm/ioapic.c
View File

@ -112,7 +112,7 @@ static void kvm_ioapic_put(IOAPICCommonState *s)
static void kvm_ioapic_reset(DeviceState *dev)
{
IOAPICCommonState *s = DO_UPCAST(IOAPICCommonState, busdev.qdev, dev);
IOAPICCommonState *s = IOAPIC_COMMON(dev);
ioapic_reset_common(dev);
kvm_ioapic_put(s);
@ -131,7 +131,7 @@ static void kvm_ioapic_init(IOAPICCommonState *s, int instance_no)
{
memory_region_init_reservation(&s->io_memory, NULL, "kvm-ioapic", 0x1000);
qdev_init_gpio_in(&s->busdev.qdev, kvm_ioapic_set_irq, IOAPIC_NUM_PINS);
qdev_init_gpio_in(DEVICE(s), kvm_ioapic_set_irq, IOAPIC_NUM_PINS);
}
static Property kvm_ioapic_properties[] = {

4
hw/i386/kvmvapic.c
View File

@ -456,7 +456,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
TPRAccess access)
{
VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
VAPICROMState *s = VAPIC(dev);
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@ -508,7 +508,7 @@ static void vapic_enable_tpr_reporting(bool enable)
static void vapic_reset(DeviceState *dev)
{
VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
VAPICROMState *s = VAPIC(dev);
if (s->state == VAPIC_ACTIVE) {
s->state = VAPIC_STANDBY;

62
hw/ide/cmd646.c
View File

@ -127,7 +127,7 @@ static uint64_t bmdma_read(void *opaque, hwaddr addr,
unsigned size)
{
BMDMAState *bm = opaque;
PCIIDEState *pci_dev = bm->pci_dev;
PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
uint32_t val;
if (size != 1) {
@ -139,16 +139,16 @@ static uint64_t bmdma_read(void *opaque, hwaddr addr,
val = bm->cmd;
break;
case 1:
val = pci_dev->dev.config[MRDMODE];
val = pci_dev->config[MRDMODE];
break;
case 2:
val = bm->status;
break;
case 3:
if (bm == &pci_dev->bmdma[0]) {
val = pci_dev->dev.config[UDIDETCR0];
if (bm == &bm->pci_dev->bmdma[0]) {
val = pci_dev->config[UDIDETCR0];
} else {
val = pci_dev->dev.config[UDIDETCR1];
val = pci_dev->config[UDIDETCR1];
}
break;
default:
@ -165,7 +165,7 @@ static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
PCIIDEState *pci_dev = bm->pci_dev;
PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
if (size != 1) {
return;
@ -179,18 +179,19 @@ static void bmdma_write(void *opaque, hwaddr addr,
bmdma_cmd_writeb(bm, val);
break;
case 1:
pci_dev->dev.config[MRDMODE] =
(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
cmd646_update_irq(pci_dev);
pci_dev->config[MRDMODE] =
(pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
cmd646_update_irq(bm->pci_dev);
break;
case 2:
bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
break;
case 3:
if (bm == &pci_dev->bmdma[0])
pci_dev->dev.config[UDIDETCR0] = val;
else
pci_dev->dev.config[UDIDETCR1] = val;
if (bm == &bm->pci_dev->bmdma[0]) {
pci_dev->config[UDIDETCR0] = val;
} else {
pci_dev->config[UDIDETCR1] = val;
}
break;
}
}
@ -222,25 +223,29 @@ static void bmdma_setup_bar(PCIIDEState *d)
registers */
static void cmd646_update_irq(PCIIDEState *d)
{
PCIDevice *pd = PCI_DEVICE(d);
int pci_level;
pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
qemu_set_irq(d->dev.irq[0], pci_level);
pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
!(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
!(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
qemu_set_irq(pd->irq[0], pci_level);
}
/* the PCI irq level is the logical OR of the two channels */
static void cmd646_set_irq(void *opaque, int channel, int level)
{
PCIIDEState *d = opaque;
PCIDevice *pd = PCI_DEVICE(d);
int irq_mask;
irq_mask = MRDMODE_INTR_CH0 << channel;
if (level)
d->dev.config[MRDMODE] |= irq_mask;
else
d->dev.config[MRDMODE] &= ~irq_mask;
if (level) {
pd->config[MRDMODE] |= irq_mask;
} else {
pd->config[MRDMODE] &= ~irq_mask;
}
cmd646_update_irq(d);
}
@ -257,8 +262,8 @@ static void cmd646_reset(void *opaque)
/* CMD646 PCI IDE controller */
static int pci_cmd646_ide_initfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
uint8_t *pci_conf = d->dev.config;
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
qemu_irq *irq;
int i;
@ -284,7 +289,7 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
for (i = 0; i < 2; i++) {
ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
ide_bus_new(&d->bus[i], DEVICE(dev), i, 2);
ide_init2(&d->bus[i], irq[i]);
bmdma_init(&d->bus[i], &d->bmdma[i], d);
@ -293,14 +298,14 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
&d->bmdma[i].dma);
}
vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
qemu_register_reset(cmd646_reset, d);
return 0;
}
static void pci_cmd646_ide_exitfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
PCIIDEState *d = PCI_IDE(dev);
unsigned i;
for (i = 0; i < 2; ++i) {
@ -347,8 +352,7 @@ static void cmd646_ide_class_init(ObjectClass *klass, void *data)
static const TypeInfo cmd646_ide_info = {
.name = "cmd646-ide",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIIDEState),
.parent = TYPE_PCI_IDE,
.class_init = cmd646_ide_class_init,
};

30
hw/ide/pci.c
View File

@ -56,13 +56,14 @@ static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
IDEState *s = bmdma_active_if(bm);
PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
struct {
uint32_t addr;
uint32_t size;
} prd;
int l, len;
pci_dma_sglist_init(&s->sg, &bm->pci_dev->dev,
pci_dma_sglist_init(&s->sg, pci_dev,
s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
s->io_buffer_size = 0;
for(;;) {
@ -71,7 +72,7 @@ static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
if (bm->cur_prd_last ||
(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
return s->io_buffer_size != 0;
pci_dma_read(&bm->pci_dev->dev, bm->cur_addr, &prd, 8);
pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
bm->cur_addr += 8;
prd.addr = le32_to_cpu(prd.addr);
prd.size = le32_to_cpu(prd.size);
@ -98,6 +99,7 @@ static int bmdma_rw_buf(IDEDMA *dma, int is_write)
{
BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
IDEState *s = bmdma_active_if(bm);
PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
struct {
uint32_t addr;
uint32_t size;
@ -113,7 +115,7 @@ static int bmdma_rw_buf(IDEDMA *dma, int is_write)
if (bm->cur_prd_last ||
(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
return 0;
pci_dma_read(&bm->pci_dev->dev, bm->cur_addr, &prd, 8);
pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
bm->cur_addr += 8;
prd.addr = le32_to_cpu(prd.addr);
prd.size = le32_to_cpu(prd.size);
@ -128,10 +130,10 @@ static int bmdma_rw_buf(IDEDMA *dma, int is_write)
l = bm->cur_prd_len;
if (l > 0) {
if (is_write) {
pci_dma_write(&bm->pci_dev->dev, bm->cur_prd_addr,
pci_dma_write(pci_dev, bm->cur_prd_addr,
s->io_buffer + s->io_buffer_index, l);
} else {
pci_dma_read(&bm->pci_dev->dev, bm->cur_prd_addr,
pci_dma_read(pci_dev, bm->cur_prd_addr,
s->io_buffer + s->io_buffer_index, l);
}
bm->cur_prd_addr += l;
@ -480,7 +482,7 @@ const VMStateDescription vmstate_ide_pci = {
.minimum_version_id_old = 0,
.post_load = ide_pci_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, PCIIDEState),
VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
vmstate_bmdma, BMDMAState),
VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
@ -492,7 +494,7 @@ const VMStateDescription vmstate_ide_pci = {
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
PCIIDEState *d = PCI_IDE(dev);
static const int bus[4] = { 0, 0, 1, 1 };
static const int unit[4] = { 0, 1, 0, 1 };
int i;
@ -531,3 +533,17 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
bus->irq = *irq;
bm->pci_dev = d;
}
static const TypeInfo pci_ide_type_info = {
.name = TYPE_PCI_IDE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIIDEState),
.abstract = true,
};
static void pci_ide_register_types(void)
{
type_register_static(&pci_ide_type_info);
}
type_init(pci_ide_register_types)

8
hw/ide/pci.h
View File

@ -37,8 +37,14 @@ typedef struct CMD646BAR {
struct PCIIDEState *pci_dev;
} CMD646BAR;
#define TYPE_PCI_IDE "pci-ide"
#define PCI_IDE(obj) OBJECT_CHECK(PCIIDEState, (obj), TYPE_PCI_IDE)
typedef struct PCIIDEState {
PCIDevice dev;
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
IDEBus bus[2];
BMDMAState bmdma[2];
uint32_t secondary; /* used only for cmd646 */

30
hw/ide/piix.c
View File

@ -106,7 +106,8 @@ static void bmdma_setup_bar(PCIIDEState *d)
static void piix3_reset(void *opaque)
{
PCIIDEState *d = opaque;
uint8_t *pci_conf = d->dev.config;
PCIDevice *pd = PCI_DEVICE(d);
uint8_t *pci_conf = pd->config;
int i;
for (i = 0; i < 2; i++) {
@ -135,7 +136,7 @@ static void pci_piix_init_ports(PCIIDEState *d) {
int i;
for (i = 0; i < 2; i++) {
ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
ide_bus_new(&d->bus[i], DEVICE(d), i, 2);
ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
@ -149,17 +150,17 @@ static void pci_piix_init_ports(PCIIDEState *d) {
static int pci_piix_ide_initfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
uint8_t *pci_conf = d->dev.config;
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
qemu_register_reset(piix3_reset, d);
bmdma_setup_bar(d);
pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
pci_piix_init_ports(d);
@ -168,13 +169,11 @@ static int pci_piix_ide_initfn(PCIDevice *dev)
static int pci_piix3_xen_ide_unplug(DeviceState *dev)
{
PCIDevice *pci_dev;
PCIIDEState *pci_ide;
DriveInfo *di;
int i = 0;
pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
pci_ide = PCI_IDE(dev);
for (; i < 3; i++) {
di = drive_get_by_index(IF_IDE, i);
@ -188,7 +187,7 @@ static int pci_piix3_xen_ide_unplug(DeviceState *dev)
drive_put_ref(di);
}
}
qdev_reset_all(&(pci_ide->dev.qdev));
qdev_reset_all(DEVICE(dev));
return 0;
}
@ -203,7 +202,7 @@ PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
static void pci_piix_ide_exitfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
PCIIDEState *d = PCI_IDE(dev);
unsigned i;
for (i = 0; i < 2; ++i) {
@ -254,8 +253,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix3_ide_info = {
.name = "piix3-ide",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIIDEState),
.parent = TYPE_PCI_IDE,
.class_init = piix3_ide_class_init,
};
@ -275,8 +273,7 @@ static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix3_ide_xen_info = {
.name = "piix3-ide-xen",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIIDEState),
.parent = TYPE_PCI_IDE,
.class_init = piix3_ide_xen_class_init,
};
@ -297,8 +294,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix4_ide_info = {
.name = "piix4-ide",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIIDEState),
.parent = TYPE_PCI_IDE,
.class_init = piix4_ide_class_init,
};

18
hw/ide/via.c
View File

@ -108,7 +108,8 @@ static void bmdma_setup_bar(PCIIDEState *d)
static void via_reset(void *opaque)
{
PCIIDEState *d = opaque;
uint8_t *pci_conf = d->dev.config;
PCIDevice *pd = PCI_DEVICE(d);
uint8_t *pci_conf = pd->config;
int i;
for (i = 0; i < 2; i++) {
@ -158,7 +159,7 @@ static void vt82c686b_init_ports(PCIIDEState *d) {
int i;
for (i = 0; i < 2; i++) {
ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
ide_bus_new(&d->bus[i], DEVICE(d), i, 2);
ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
@ -173,17 +174,17 @@ static void vt82c686b_init_ports(PCIIDEState *d) {
/* via ide func */
static int vt82c686b_ide_initfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
uint8_t *pci_conf = d->dev.config;
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
qemu_register_reset(via_reset, d);
bmdma_setup_bar(d);
pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
vt82c686b_init_ports(d);
@ -192,7 +193,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
static void vt82c686b_ide_exitfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
PCIIDEState *d = PCI_IDE(dev);
unsigned i;
for (i = 0; i < 2; ++i) {
@ -229,8 +230,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data)
static const TypeInfo via_ide_info = {
.name = "via-ide",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIIDEState),
.parent = TYPE_PCI_IDE,
.class_init = via_ide_class_init,
};

14
hw/input/milkymist-softusb.c
View File

@ -44,8 +44,13 @@ enum {
#define COMLOC_KEVT_PRODUCE 0x1142
#define COMLOC_KEVT_BASE 0x1143
#define TYPE_MILKYMIST_SOFTUSB "milkymist-softusb"
#define MILKYMIST_SOFTUSB(obj) \
OBJECT_CHECK(MilkymistSoftUsbState, (obj), TYPE_MILKYMIST_SOFTUSB)
struct MilkymistSoftUsbState {
SysBusDevice busdev;
SysBusDevice parent_obj;
HIDState hid_kbd;
HIDState hid_mouse;
@ -242,8 +247,7 @@ static void softusb_mouse_hid_datain(HIDState *hs)
static void milkymist_softusb_reset(DeviceState *d)
{
MilkymistSoftUsbState *s =
container_of(d, MilkymistSoftUsbState, busdev.qdev);
MilkymistSoftUsbState *s = MILKYMIST_SOFTUSB(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -261,7 +265,7 @@ static void milkymist_softusb_reset(DeviceState *d)
static int milkymist_softusb_init(SysBusDevice *dev)
{
MilkymistSoftUsbState *s = FROM_SYSBUS(typeof(*s), dev);
MilkymistSoftUsbState *s = MILKYMIST_SOFTUSB(dev);
sysbus_init_irq(dev, &s->irq);
@ -320,7 +324,7 @@ static void milkymist_softusb_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_softusb_info = {
.name = "milkymist-softusb",
.name = TYPE_MILKYMIST_SOFTUSB,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistSoftUsbState),
.class_init = milkymist_softusb_class_init,

90
hw/input/pl050.c
View File

@ -10,8 +10,12 @@
#include "hw/sysbus.h"
#include "hw/input/ps2.h"
typedef struct {
SysBusDevice busdev;
#define TYPE_PL050 "pl050"
#define PL050(obj) OBJECT_CHECK(PL050State, (obj), TYPE_PL050)
typedef struct PL050State {
SysBusDevice parent_obj;
MemoryRegion iomem;
void *dev;
uint32_t cr;
@ -19,18 +23,18 @@ typedef struct {
uint32_t last;
int pending;
qemu_irq irq;
int is_mouse;
} pl050_state;
bool is_mouse;
} PL050State;
static const VMStateDescription vmstate_pl050 = {
.name = "pl050",
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cr, pl050_state),
VMSTATE_UINT32(clk, pl050_state),
VMSTATE_UINT32(last, pl050_state),
VMSTATE_INT32(pending, pl050_state),
VMSTATE_UINT32(cr, PL050State),
VMSTATE_UINT32(clk, PL050State),
VMSTATE_UINT32(last, PL050State),
VMSTATE_INT32(pending, PL050State),
VMSTATE_END_OF_LIST()
}
};
@ -48,7 +52,7 @@ static const unsigned char pl050_id[] =
static void pl050_update(void *opaque, int level)
{
pl050_state *s = (pl050_state *)opaque;
PL050State *s = (PL050State *)opaque;
int raise;
s->pending = level;
@ -60,7 +64,7 @@ static void pl050_update(void *opaque, int level)
static uint64_t pl050_read(void *opaque, hwaddr offset,
unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
PL050State *s = (PL050State *)opaque;
if (offset >= 0xfe0 && offset < 0x1000)
return pl050_id[(offset - 0xfe0) >> 2];
@ -103,7 +107,7 @@ static uint64_t pl050_read(void *opaque, hwaddr offset,
static void pl050_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
PL050State *s = (PL050State *)opaque;
switch (offset >> 2) {
case 0: /* KMICR */
s->cr = value;
@ -133,65 +137,67 @@ static const MemoryRegionOps pl050_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int pl050_init(SysBusDevice *dev, int is_mouse)
static int pl050_initfn(SysBusDevice *dev)
{
pl050_state *s = FROM_SYSBUS(pl050_state, dev);
PL050State *s = PL050(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->is_mouse = is_mouse;
if (s->is_mouse)
if (s->is_mouse) {
s->dev = ps2_mouse_init(pl050_update, s);
else
} else {
s->dev = ps2_kbd_init(pl050_update, s);
}
return 0;
}
static int pl050_init_keyboard(SysBusDevice *dev)
static void pl050_keyboard_init(Object *obj)
{
return pl050_init(dev, 0);
PL050State *s = PL050(obj);
s->is_mouse = false;
}
static int pl050_init_mouse(SysBusDevice *dev)
static void pl050_mouse_init(Object *obj)
{
return pl050_init(dev, 1);
}
PL050State *s = PL050(obj);
static void pl050_kbd_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl050_init_keyboard;
dc->vmsd = &vmstate_pl050;
s->is_mouse = true;
}
static const TypeInfo pl050_kbd_info = {
.name = "pl050_keyboard",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl050_state),
.class_init = pl050_kbd_class_init,
.parent = TYPE_PL050,
.instance_init = pl050_keyboard_init,
};
static void pl050_mouse_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = pl050_init_mouse;
dc->vmsd = &vmstate_pl050;
}
static const TypeInfo pl050_mouse_info = {
.name = "pl050_mouse",
.parent = TYPE_PL050,
.instance_init = pl050_mouse_init,
};
static void pl050_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(oc);
sdc->init = pl050_initfn;
dc->vmsd = &vmstate_pl050;
}
static const TypeInfo pl050_type_info = {
.name = TYPE_PL050,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl050_state),
.class_init = pl050_mouse_class_init,
.instance_size = sizeof(PL050State),
.abstract = true,
.class_init = pl050_class_init,
};
static void pl050_register_types(void)
{
type_register_static(&pl050_type_info);
type_register_static(&pl050_kbd_info);
type_register_static(&pl050_mouse_info);
}

5
hw/intc/arm_gic.c
View File

@ -639,6 +639,7 @@ static const MemoryRegionOps gic_cpu_ops = {
void gic_init_irqs_and_distributor(GICState *s, int num_irq)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
int i;
i = s->num_irq - GIC_INTERNAL;
@ -652,9 +653,9 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq)
if (s->revision != REV_NVIC) {
i += (GIC_INTERNAL * s->num_cpu);
}
qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i);
qdev_init_gpio_in(DEVICE(s), gic_set_irq, i);
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
sysbus_init_irq(sbd, &s->parent_irq[i]);
}
memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s,
"gic_dist", 0x1000);

2
hw/intc/arm_gic_common.c
View File

@ -110,7 +110,7 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
static void arm_gic_common_reset(DeviceState *dev)
{
GICState *s = FROM_SYSBUS(GICState, SYS_BUS_DEVICE(dev));
GICState *s = ARM_GIC_COMMON(dev);
int i;
memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
for (i = 0 ; i < s->num_cpu; i++) {

22
hw/intc/etraxfs_pic.c
View File

@ -36,9 +36,14 @@
#define R_R_GURU 4
#define R_MAX 5
#define TYPE_ETRAX_FS_PIC "etraxfs,pic"
#define ETRAX_FS_PIC(obj) \
OBJECT_CHECK(struct etrax_pic, (obj), TYPE_ETRAX_FS_PIC)
struct etrax_pic
{
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion mmio;
void *interrupt_vector;
qemu_irq parent_irq;
@ -138,17 +143,18 @@ static void irq_handler(void *opaque, int irq, int level)
pic_update(fs);
}
static int etraxfs_pic_init(SysBusDevice *dev)
static int etraxfs_pic_init(SysBusDevice *sbd)
{
struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev);
DeviceState *dev = DEVICE(sbd);
struct etrax_pic *s = ETRAX_FS_PIC(dev);
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_nmi);
qdev_init_gpio_in(dev, irq_handler, 32);
sysbus_init_irq(sbd, &s->parent_irq);
sysbus_init_irq(sbd, &s->parent_nmi);
memory_region_init_io(&s->mmio, OBJECT(s), &pic_ops, s,
"etraxfs-pic", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_mmio(sbd, &s->mmio);
return 0;
}
@ -167,7 +173,7 @@ static void etraxfs_pic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo etraxfs_pic_info = {
.name = "etraxfs,pic",
.name = TYPE_ETRAX_FS_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct etrax_pic),
.class_init = etraxfs_pic_class_init,

23
hw/intc/exynos4210_combiner.c
View File

@ -56,8 +56,13 @@ typedef struct CombinerGroupState {
uint8_t src_pending; /* Pending source interrupts before masking */
} CombinerGroupState;
#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
#define EXYNOS4210_COMBINER(obj) \
OBJECT_CHECK(Exynos4210CombinerState, (obj), TYPE_EXYNOS4210_COMBINER)
typedef struct Exynos4210CombinerState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
struct CombinerGroupState group[IIC_NGRP];
@ -402,24 +407,24 @@ static const MemoryRegionOps exynos4210_combiner_ops = {
/*
* Internal Combiner initialization.
*/
static int exynos4210_combiner_init(SysBusDevice *dev)
static int exynos4210_combiner_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
Exynos4210CombinerState *s = EXYNOS4210_COMBINER(dev);
unsigned int i;
struct Exynos4210CombinerState *s =
FROM_SYSBUS(struct Exynos4210CombinerState, dev);
/* Allocate general purpose input signals and connect a handler to each of
* them */
qdev_init_gpio_in(&s->busdev.qdev, exynos4210_combiner_handler, IIC_NIRQ);
qdev_init_gpio_in(dev, exynos4210_combiner_handler, IIC_NIRQ);
/* Connect SysBusDev irqs to device specific irqs */
for (i = 0; i < IIC_NIRQ; i++) {
sysbus_init_irq(dev, &s->output_irq[i]);
sysbus_init_irq(sbd, &s->output_irq[i]);
}
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_combiner_ops, s,
"exynos4210-combiner", IIC_REGION_SIZE);
sysbus_init_mmio(dev, &s->iomem);
"exynos4210-combiner", IIC_REGION_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -441,7 +446,7 @@ static void exynos4210_combiner_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo exynos4210_combiner_info = {
.name = "exynos4210.combiner",
.name = TYPE_EXYNOS4210_COMBINER,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210CombinerState),
.class_init = exynos4210_combiner_class_init,

45
hw/intc/exynos4210_gic.c
View File

@ -260,8 +260,13 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
/********* GIC part *********/
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
#define EXYNOS4210_GIC(obj) \
OBJECT_CHECK(Exynos4210GicState, (obj), TYPE_EXYNOS4210_GIC)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion cpu_container;
MemoryRegion dist_container;
MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
@ -276,9 +281,10 @@ static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
}
static int exynos4210_gic_init(SysBusDevice *dev)
static int exynos4210_gic_init(SysBusDevice *sbd)
{
Exynos4210GicState *s = FROM_SYSBUS(Exynos4210GicState, dev);
DeviceState *dev = DEVICE(sbd);
Exynos4210GicState *s = EXYNOS4210_GIC(dev);
uint32_t i;
const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
const char dist_prefix[] = "exynos4210-gic-alias_dist";
@ -293,10 +299,10 @@ static int exynos4210_gic_init(SysBusDevice *dev)
busdev = SYS_BUS_DEVICE(s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, busdev);
sysbus_pass_irq(sbd, busdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, exynos4210_gic_set_irq,
qdev_init_gpio_in(dev, exynos4210_gic_set_irq,
EXYNOS4210_GIC_NIRQ - 32);
memory_region_init(&s->cpu_container, OBJECT(s), "exynos4210-cpu-container",
@ -326,8 +332,8 @@ static int exynos4210_gic_init(SysBusDevice *dev)
EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]);
}
sysbus_init_mmio(dev, &s->cpu_container);
sysbus_init_mmio(dev, &s->dist_container);
sysbus_init_mmio(sbd, &s->cpu_container);
sysbus_init_mmio(sbd, &s->dist_container);
return 0;
}
@ -347,7 +353,7 @@ static void exynos4210_gic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo exynos4210_gic_info = {
.name = "exynos4210.gic",
.name = TYPE_EXYNOS4210_GIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210GicState),
.class_init = exynos4210_gic_class_init,
@ -366,8 +372,13 @@ type_init(exynos4210_gic_register_types)
* output sysbus IRQ line. The output IRQ level is formed as OR between all
* gpio inputs.
*/
typedef struct {
SysBusDevice busdev;
#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
#define EXYNOS4210_IRQ_GATE(obj) \
OBJECT_CHECK(Exynos4210IRQGateState, (obj), TYPE_EXYNOS4210_IRQ_GATE)
typedef struct Exynos4210IRQGateState {
SysBusDevice parent_obj;
uint32_t n_in; /* inputs amount */
uint32_t *level; /* input levels */
@ -412,8 +423,7 @@ static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
static void exynos4210_irq_gate_reset(DeviceState *d)
{
Exynos4210IRQGateState *s =
DO_UPCAST(Exynos4210IRQGateState, busdev.qdev, d);
Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
memset(s->level, 0, s->n_in * sizeof(*s->level));
}
@ -421,17 +431,18 @@ static void exynos4210_irq_gate_reset(DeviceState *d)
/*
* IRQ Gate initialization.
*/
static int exynos4210_irq_gate_init(SysBusDevice *dev)
static int exynos4210_irq_gate_init(SysBusDevice *sbd)
{
Exynos4210IRQGateState *s = FROM_SYSBUS(Exynos4210IRQGateState, dev);
DeviceState *dev = DEVICE(sbd);
Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
/* Allocate general purpose input signals and connect a handler to each of
* them */
qdev_init_gpio_in(&s->busdev.qdev, exynos4210_irq_gate_handler, s->n_in);
qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
s->level = g_malloc0(s->n_in * sizeof(*s->level));
sysbus_init_irq(dev, &s->out);
sysbus_init_irq(sbd, &s->out);
return 0;
}
@ -448,7 +459,7 @@ static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo exynos4210_irq_gate_info = {
.name = "exynos4210.irq_gate",
.name = TYPE_EXYNOS4210_IRQ_GATE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210IRQGateState),
.class_init = exynos4210_irq_gate_class_init,

5
hw/intc/gic_internal.h
View File

@ -70,7 +70,10 @@ typedef struct gic_irq_state {
} gic_irq_state;
typedef struct GICState {
SysBusDevice busdev;
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
qemu_irq parent_irq[NCPU];
bool enabled;
bool cpu_enabled[NCPU];

33
hw/intc/grlib_irqmp.c
View File

@ -45,10 +45,14 @@
#define FORCE_OFFSET 0x80
#define EXTENDED_OFFSET 0xC0
#define TYPE_GRLIB_IRQMP "grlib,irqmp"
#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
typedef struct IRQMPState IRQMPState;
typedef struct IRQMP {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
void *set_pil_in;
@ -102,19 +106,10 @@ static void grlib_irqmp_check_irqs(IRQMPState *state)
void grlib_irqmp_ack(DeviceState *dev, int intno)
{
SysBusDevice *sdev;
IRQMP *irqmp;
IRQMP *irqmp = GRLIB_IRQMP(dev);
IRQMPState *state;
uint32_t mask;
assert(dev != NULL);
sdev = SYS_BUS_DEVICE(dev);
assert(sdev != NULL);
irqmp = FROM_SYSBUS(typeof(*irqmp), sdev);
assert(irqmp != NULL);
state = irqmp->state;
assert(state != NULL);
@ -132,15 +127,10 @@ void grlib_irqmp_ack(DeviceState *dev, int intno)
void grlib_irqmp_set_irq(void *opaque, int irq, int level)
{
IRQMP *irqmp;
IRQMP *irqmp = GRLIB_IRQMP(opaque);
IRQMPState *s;
int i = 0;
assert(opaque != NULL);
irqmp = FROM_SYSBUS(typeof(*irqmp), SYS_BUS_DEVICE(opaque));
assert(irqmp != NULL);
s = irqmp->state;
assert(s != NULL);
assert(s->parent != NULL);
@ -325,8 +315,7 @@ static const MemoryRegionOps grlib_irqmp_ops = {
static void grlib_irqmp_reset(DeviceState *d)
{
IRQMP *irqmp = container_of(d, IRQMP, busdev.qdev);
assert(irqmp != NULL);
IRQMP *irqmp = GRLIB_IRQMP(d);
assert(irqmp->state != NULL);
memset(irqmp->state, 0, sizeof *irqmp->state);
@ -335,9 +324,7 @@ static void grlib_irqmp_reset(DeviceState *d)
static int grlib_irqmp_init(SysBusDevice *dev)
{
IRQMP *irqmp = FROM_SYSBUS(typeof(*irqmp), dev);
assert(irqmp != NULL);
IRQMP *irqmp = GRLIB_IRQMP(dev);
/* Check parameters */
if (irqmp->set_pil_in == NULL) {
@ -371,7 +358,7 @@ static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo grlib_irqmp_info = {
.name = "grlib,irqmp",
.name = TYPE_GRLIB_IRQMP,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IRQMP),
.class_init = grlib_irqmp_class_init,

27
hw/intc/imx_avic.c
View File

@ -55,8 +55,13 @@ do { printf("imx_avic: " fmt , ##args); } while (0)
#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
typedef struct {
SysBusDevice busdev;
#define TYPE_IMX_AVIC "imx_avic"
#define IMX_AVIC(obj) \
OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
typedef struct IMXAVICState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint64_t pending;
uint64_t enabled;
@ -359,7 +364,8 @@ static const MemoryRegionOps imx_avic_ops = {
static void imx_avic_reset(DeviceState *dev)
{
IMXAVICState *s = container_of(dev, IMXAVICState, busdev.qdev);
IMXAVICState *s = IMX_AVIC(dev);
s->pending = 0;
s->enabled = 0;
s->is_fiq = 0;
@ -368,17 +374,18 @@ static void imx_avic_reset(DeviceState *dev)
memset(s->prio, 0, sizeof s->prio);
}
static int imx_avic_init(SysBusDevice *dev)
static int imx_avic_init(SysBusDevice *sbd)
{
IMXAVICState *s = FROM_SYSBUS(IMXAVICState, dev);
DeviceState *dev = DEVICE(sbd);
IMXAVICState *s = IMX_AVIC(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s,
"imx_avic", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_in(&dev->qdev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->fiq);
qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->fiq);
return 0;
}
@ -395,7 +402,7 @@ static void imx_avic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo imx_avic_info = {
.name = "imx_avic",
.name = TYPE_IMX_AVIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMXAVICState),
.class_init = imx_avic_class_init,

2
hw/intc/ioapic.c
View File

@ -230,7 +230,7 @@ static void ioapic_init(IOAPICCommonState *s, int instance_no)
memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
"ioapic", 0x1000);
qdev_init_gpio_in(&s->busdev.qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
qdev_init_gpio_in(DEVICE(s), ioapic_set_irq, IOAPIC_NUM_PINS);
ioapics[instance_no] = s;
}

27
hw/intc/lm32_pic.c
View File

@ -26,8 +26,12 @@
#include "trace.h"
#include "hw/lm32/lm32_pic.h"
#define TYPE_LM32_PIC "lm32-pic"
#define LM32_PIC(obj) OBJECT_CHECK(LM32PicState, (obj), TYPE_LM32_PIC)
struct LM32PicState {
SysBusDevice busdev;
SysBusDevice parent_obj;
qemu_irq parent_irq;
uint32_t im; /* interrupt mask */
uint32_t ip; /* interrupt pending */
@ -99,7 +103,7 @@ static void irq_handler(void *opaque, int irq, int level)
void lm32_pic_set_im(DeviceState *d, uint32_t im)
{
LM32PicState *s = container_of(d, LM32PicState, busdev.qdev);
LM32PicState *s = LM32_PIC(d);
trace_lm32_pic_set_im(im);
s->im = im;
@ -109,7 +113,7 @@ void lm32_pic_set_im(DeviceState *d, uint32_t im)
void lm32_pic_set_ip(DeviceState *d, uint32_t ip)
{
LM32PicState *s = container_of(d, LM32PicState, busdev.qdev);
LM32PicState *s = LM32_PIC(d);
trace_lm32_pic_set_ip(ip);
@ -121,7 +125,7 @@ void lm32_pic_set_ip(DeviceState *d, uint32_t ip)
uint32_t lm32_pic_get_im(DeviceState *d)
{
LM32PicState *s = container_of(d, LM32PicState, busdev.qdev);
LM32PicState *s = LM32_PIC(d);
trace_lm32_pic_get_im(s->im);
return s->im;
@ -129,7 +133,7 @@ uint32_t lm32_pic_get_im(DeviceState *d)
uint32_t lm32_pic_get_ip(DeviceState *d)
{
LM32PicState *s = container_of(d, LM32PicState, busdev.qdev);
LM32PicState *s = LM32_PIC(d);
trace_lm32_pic_get_ip(s->ip);
return s->ip;
@ -137,7 +141,7 @@ uint32_t lm32_pic_get_ip(DeviceState *d)
static void pic_reset(DeviceState *d)
{
LM32PicState *s = container_of(d, LM32PicState, busdev.qdev);
LM32PicState *s = LM32_PIC(d);
int i;
s->im = 0;
@ -148,12 +152,13 @@ static void pic_reset(DeviceState *d)
}
}
static int lm32_pic_init(SysBusDevice *dev)
static int lm32_pic_init(SysBusDevice *sbd)
{
LM32PicState *s = FROM_SYSBUS(typeof(*s), dev);
DeviceState *dev = DEVICE(sbd);
LM32PicState *s = LM32_PIC(dev);
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &s->parent_irq);
qdev_init_gpio_in(dev, irq_handler, 32);
sysbus_init_irq(sbd, &s->parent_irq);
pic = s;
@ -185,7 +190,7 @@ static void lm32_pic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo lm32_pic_info = {
.name = "lm32-pic",
.name = TYPE_LM32_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LM32PicState),
.class_init = lm32_pic_class_init,

57
hw/intc/omap_intc.c
View File

@ -32,8 +32,13 @@ struct omap_intr_handler_bank_s {
unsigned char priority[32];
};
#define TYPE_OMAP_INTC "common-omap-intc"
#define OMAP_INTC(obj) \
OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
struct omap_intr_handler_s {
SysBusDevice busdev;
SysBusDevice parent_obj;
qemu_irq *pins;
qemu_irq parent_intr[2];
MemoryRegion mmio;
@ -328,8 +333,7 @@ static const MemoryRegionOps omap_inth_mem_ops = {
static void omap_inth_reset(DeviceState *dev)
{
struct omap_intr_handler_s *s = FROM_SYSBUS(struct omap_intr_handler_s,
SYS_BUS_DEVICE(dev));
struct omap_intr_handler_s *s = OMAP_INTC(dev);
int i;
for (i = 0; i < s->nbanks; ++i){
@ -356,20 +360,21 @@ static void omap_inth_reset(DeviceState *dev)
qemu_set_irq(s->parent_intr[1], 0);
}
static int omap_intc_init(SysBusDevice *dev)
static int omap_intc_init(SysBusDevice *sbd)
{
struct omap_intr_handler_s *s;
s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
DeviceState *dev = DEVICE(sbd);
struct omap_intr_handler_s *s = OMAP_INTC(dev);
if (!s->iclk) {
hw_error("omap-intc: clk not connected\n");
}
s->nbanks = 1;
sysbus_init_irq(dev, &s->parent_intr[0]);
sysbus_init_irq(dev, &s->parent_intr[1]);
qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
sysbus_init_irq(sbd, &s->parent_intr[0]);
sysbus_init_irq(sbd, &s->parent_intr[1]);
qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
memory_region_init_io(&s->mmio, OBJECT(s), &omap_inth_mem_ops, s,
"omap-intc", s->size);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_mmio(sbd, &s->mmio);
return 0;
}
@ -391,8 +396,7 @@ static void omap_intc_class_init(ObjectClass *klass, void *data)
static const TypeInfo omap_intc_info = {
.name = "omap-intc",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap_intr_handler_s),
.parent = TYPE_OMAP_INTC,
.class_init = omap_intc_class_init,
};
@ -500,8 +504,9 @@ static void omap2_inth_write(void *opaque, hwaddr addr,
case 0x10: /* INTC_SYSCONFIG */
s->autoidle &= 4;
s->autoidle |= (value & 1) << 2;
if (value & 2) /* SOFTRESET */
omap_inth_reset(&s->busdev.qdev);
if (value & 2) { /* SOFTRESET */
omap_inth_reset(DEVICE(s));
}
return;
case 0x48: /* INTC_CONTROL */
@ -594,10 +599,11 @@ static const MemoryRegionOps omap2_inth_mem_ops = {
},
};
static int omap2_intc_init(SysBusDevice *dev)
static int omap2_intc_init(SysBusDevice *sbd)
{
struct omap_intr_handler_s *s;
s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
DeviceState *dev = DEVICE(sbd);
struct omap_intr_handler_s *s = OMAP_INTC(dev);
if (!s->iclk) {
hw_error("omap2-intc: iclk not connected\n");
}
@ -606,12 +612,12 @@ static int omap2_intc_init(SysBusDevice *dev)
}
s->level_only = 1;
s->nbanks = 3;
sysbus_init_irq(dev, &s->parent_intr[0]);
sysbus_init_irq(dev, &s->parent_intr[1]);
qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
sysbus_init_irq(sbd, &s->parent_intr[0]);
sysbus_init_irq(sbd, &s->parent_intr[1]);
qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
memory_region_init_io(&s->mmio, OBJECT(s), &omap2_inth_mem_ops, s,
"omap2-intc", 0x1000);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_mmio(sbd, &s->mmio);
return 0;
}
@ -635,13 +641,20 @@ static void omap2_intc_class_init(ObjectClass *klass, void *data)
static const TypeInfo omap2_intc_info = {
.name = "omap2-intc",
.parent = TYPE_OMAP_INTC,
.class_init = omap2_intc_class_init,
};
static const TypeInfo omap_intc_type_info = {
.name = TYPE_OMAP_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap_intr_handler_s),
.class_init = omap2_intc_class_init,
.abstract = true,
};
static void omap_intc_register_types(void)
{
type_register_static(&omap_intc_type_info);
type_register_static(&omap_intc_info);
type_register_static(&omap2_intc_info);
}

78
hw/intc/pl190.c
View File

@ -15,8 +15,12 @@
#define PL190_NUM_PRIO 17
typedef struct {
SysBusDevice busdev;
#define TYPE_PL190 "pl190"
#define PL190(obj) OBJECT_CHECK(PL190State, (obj), TYPE_PL190)
typedef struct PL190State {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t level;
uint32_t soft_level;
@ -32,18 +36,18 @@ typedef struct {
int prev_prio[PL190_NUM_PRIO];
qemu_irq irq;
qemu_irq fiq;
} pl190_state;
} PL190State;
static const unsigned char pl190_id[] =
{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
static inline uint32_t pl190_irq_level(pl190_state *s)
static inline uint32_t pl190_irq_level(PL190State *s)
{
return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
}
/* Update interrupts. */
static void pl190_update(pl190_state *s)
static void pl190_update(PL190State *s)
{
uint32_t level = pl190_irq_level(s);
int set;
@ -56,7 +60,7 @@ static void pl190_update(pl190_state *s)
static void pl190_set_irq(void *opaque, int irq, int level)
{
pl190_state *s = (pl190_state *)opaque;
PL190State *s = (PL190State *)opaque;
if (level)
s->level |= 1u << irq;
@ -65,7 +69,7 @@ static void pl190_set_irq(void *opaque, int irq, int level)
pl190_update(s);
}
static void pl190_update_vectors(pl190_state *s)
static void pl190_update_vectors(PL190State *s)
{
uint32_t mask;
int i;
@ -88,7 +92,7 @@ static void pl190_update_vectors(pl190_state *s)
static uint64_t pl190_read(void *opaque, hwaddr offset,
unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
PL190State *s = (PL190State *)opaque;
int i;
if (offset >= 0xfe0 && offset < 0x1000) {
@ -152,7 +156,7 @@ static uint64_t pl190_read(void *opaque, hwaddr offset,
static void pl190_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
PL190State *s = (PL190State *)opaque;
if (offset >= 0x100 && offset < 0x140) {
s->vect_addr[(offset - 0x100) >> 2] = val;
@ -218,29 +222,29 @@ static const MemoryRegionOps pl190_ops = {
static void pl190_reset(DeviceState *d)
{
pl190_state *s = DO_UPCAST(pl190_state, busdev.qdev, d);
int i;
PL190State *s = PL190(d);
int i;
for (i = 0; i < 16; i++)
{
s->vect_addr[i] = 0;
s->vect_control[i] = 0;
for (i = 0; i < 16; i++) {
s->vect_addr[i] = 0;
s->vect_control[i] = 0;
}
s->vect_addr[16] = 0;
s->prio_mask[17] = 0xffffffff;
s->priority = PL190_NUM_PRIO;
pl190_update_vectors(s);
s->vect_addr[16] = 0;
s->prio_mask[17] = 0xffffffff;
s->priority = PL190_NUM_PRIO;
pl190_update_vectors(s);
}
static int pl190_init(SysBusDevice *dev)
static int pl190_init(SysBusDevice *sbd)
{
pl190_state *s = FROM_SYSBUS(pl190_state, dev);
DeviceState *dev = DEVICE(sbd);
PL190State *s = PL190(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &pl190_ops, s, "pl190", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->fiq);
sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_in(dev, pl190_set_irq, 32);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->fiq);
return 0;
}
@ -249,16 +253,16 @@ static const VMStateDescription vmstate_pl190 = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(level, pl190_state),
VMSTATE_UINT32(soft_level, pl190_state),
VMSTATE_UINT32(irq_enable, pl190_state),
VMSTATE_UINT32(fiq_select, pl190_state),
VMSTATE_UINT8_ARRAY(vect_control, pl190_state, 16),
VMSTATE_UINT32_ARRAY(vect_addr, pl190_state, PL190_NUM_PRIO),
VMSTATE_UINT32_ARRAY(prio_mask, pl190_state, PL190_NUM_PRIO+1),
VMSTATE_INT32(protected, pl190_state),
VMSTATE_INT32(priority, pl190_state),
VMSTATE_INT32_ARRAY(prev_prio, pl190_state, PL190_NUM_PRIO),
VMSTATE_UINT32(level, PL190State),
VMSTATE_UINT32(soft_level, PL190State),
VMSTATE_UINT32(irq_enable, PL190State),
VMSTATE_UINT32(fiq_select, PL190State),
VMSTATE_UINT8_ARRAY(vect_control, PL190State, 16),
VMSTATE_UINT32_ARRAY(vect_addr, PL190State, PL190_NUM_PRIO),
VMSTATE_UINT32_ARRAY(prio_mask, PL190State, PL190_NUM_PRIO+1),
VMSTATE_INT32(protected, PL190State),
VMSTATE_INT32(priority, PL190State),
VMSTATE_INT32_ARRAY(prev_prio, PL190State, PL190_NUM_PRIO),
VMSTATE_END_OF_LIST()
}
};
@ -275,9 +279,9 @@ static void pl190_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo pl190_info = {
.name = "pl190",
.name = TYPE_PL190,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl190_state),
.instance_size = sizeof(PL190State),
.class_init = pl190_class_init,
};

23
hw/intc/puv3_intc.c
View File

@ -13,8 +13,12 @@
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
typedef struct {
SysBusDevice busdev;
#define TYPE_PUV3_INTC "puv3_intc"
#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
typedef struct PUV3INTCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq parent_irq;
@ -96,19 +100,20 @@ static const MemoryRegionOps puv3_intc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int puv3_intc_init(SysBusDevice *dev)
static int puv3_intc_init(SysBusDevice *sbd)
{
PUV3INTCState *s = FROM_SYSBUS(PUV3INTCState, dev);
DeviceState *dev = DEVICE(sbd);
PUV3INTCState *s = PUV3_INTC(dev);
qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
sysbus_init_irq(&s->busdev, &s->parent_irq);
qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
sysbus_init_irq(sbd, &s->parent_irq);
s->reg_ICMR = 0;
s->reg_ICPR = 0;
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);
PUV3_REGS_OFFSET);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
@ -121,7 +126,7 @@ static void puv3_intc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo puv3_intc_info = {
.name = "puv3_intc",
.name = TYPE_PUV3_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PUV3INTCState),
.class_init = puv3_intc_class_init,

20
hw/intc/realview_gic.c
View File

@ -9,8 +9,13 @@
#include "hw/sysbus.h"
#define TYPE_REALVIEW_GIC "realview_gic"
#define REALVIEW_GIC(obj) \
OBJECT_CHECK(RealViewGICState, (obj), TYPE_REALVIEW_GIC)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
DeviceState *gic;
MemoryRegion container;
} RealViewGICState;
@ -21,9 +26,10 @@ static void realview_gic_set_irq(void *opaque, int irq, int level)
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
}
static int realview_gic_init(SysBusDevice *dev)
static int realview_gic_init(SysBusDevice *sbd)
{
RealViewGICState *s = FROM_SYSBUS(RealViewGICState, dev);
DeviceState *dev = DEVICE(sbd);
RealViewGICState *s = REALVIEW_GIC(dev);
SysBusDevice *busdev;
/* The GICs on the RealView boards have a fixed nonconfigurable
* number of interrupt lines, so we don't need to expose this as
@ -38,10 +44,10 @@ static int realview_gic_init(SysBusDevice *dev)
busdev = SYS_BUS_DEVICE(s->gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, busdev);
sysbus_pass_irq(sbd, busdev);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(&s->busdev.qdev, realview_gic_set_irq, numirq - 32);
qdev_init_gpio_in(dev, realview_gic_set_irq, numirq - 32);
memory_region_init(&s->container, OBJECT(s),
"realview-gic-container", 0x2000);
@ -49,7 +55,7 @@ static int realview_gic_init(SysBusDevice *dev)
sysbus_mmio_get_region(busdev, 1));
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
sysbus_init_mmio(dev, &s->container);
sysbus_init_mmio(sbd, &s->container);
return 0;
}
@ -61,7 +67,7 @@ static void realview_gic_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo realview_gic_info = {
.name = "realview_gic",
.name = TYPE_REALVIEW_GIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(RealViewGICState),
.class_init = realview_gic_class_init,

35
hw/intc/slavio_intctl.c
View File

@ -53,8 +53,13 @@ typedef struct SLAVIO_CPUINTCTLState {
uint32_t irl_out;
} SLAVIO_CPUINTCTLState;
#define TYPE_SLAVIO_INTCTL "slavio_intctl"
#define SLAVIO_INTCTL(obj) \
OBJECT_CHECK(SLAVIO_INTCTLState, (obj), TYPE_SLAVIO_INTCTL)
typedef struct SLAVIO_INTCTLState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
#ifdef DEBUG_IRQ_COUNT
uint64_t irq_count[32];
@ -206,12 +211,9 @@ static const MemoryRegionOps slavio_intctlm_mem_ops = {
void slavio_pic_info(Monitor *mon, DeviceState *dev)
{
SysBusDevice *sd;
SLAVIO_INTCTLState *s;
SLAVIO_INTCTLState *s = SLAVIO_INTCTL(dev);
int i;
sd = SYS_BUS_DEVICE(dev);
s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
for (i = 0; i < MAX_CPUS; i++) {
monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
s->slaves[i].intreg_pending);
@ -225,13 +227,11 @@ void slavio_irq_info(Monitor *mon, DeviceState *dev)
#ifndef DEBUG_IRQ_COUNT
monitor_printf(mon, "irq statistic code not compiled.\n");
#else
SysBusDevice *sd;
SLAVIO_INTCTLState *s;
SLAVIO_INTCTLState *s = SLAVIO_INTCTL(dev);
int i;
int64_t count;
sd = SYS_BUS_DEVICE(dev);
s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
s = SLAVIO_INTCTL(dev);
monitor_printf(mon, "IRQ statistics:\n");
for (i = 0; i < 32; i++) {
count = s->irq_count[i];
@ -406,7 +406,7 @@ static const VMStateDescription vmstate_intctl = {
static void slavio_intctl_reset(DeviceState *d)
{
SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev);
SLAVIO_INTCTLState *s = SLAVIO_INTCTL(d);
int i;
for (i = 0; i < MAX_CPUS; i++) {
@ -419,27 +419,28 @@ static void slavio_intctl_reset(DeviceState *d)
slavio_check_interrupts(s, 0);
}
static int slavio_intctl_init1(SysBusDevice *dev)
static int slavio_intctl_init1(SysBusDevice *sbd)
{
SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
DeviceState *dev = DEVICE(sbd);
SLAVIO_INTCTLState *s = SLAVIO_INTCTL(dev);
unsigned int i, j;
char slave_name[45];
qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
qdev_init_gpio_in(dev, slavio_set_irq_all, 32 + MAX_CPUS);
memory_region_init_io(&s->iomem, OBJECT(s), &slavio_intctlm_mem_ops, s,
"master-interrupt-controller", INTCTLM_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(sbd, &s->iomem);
for (i = 0; i < MAX_CPUS; i++) {
snprintf(slave_name, sizeof(slave_name),
"slave-interrupt-controller-%i", i);
for (j = 0; j < MAX_PILS; j++) {
sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
sysbus_init_irq(sbd, &s->cpu_irqs[i][j]);
}
memory_region_init_io(&s->slaves[i].iomem, OBJECT(s),
&slavio_intctl_mem_ops,
&s->slaves[i], slave_name, INTCTL_SIZE);
sysbus_init_mmio(dev, &s->slaves[i].iomem);
sysbus_init_mmio(sbd, &s->slaves[i].iomem);
s->slaves[i].cpu = i;
s->slaves[i].master = s;
}
@ -458,7 +459,7 @@ static void slavio_intctl_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo slavio_intctl_info = {
.name = "slavio_intctl",
.name = TYPE_SLAVIO_INTCTL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SLAVIO_INTCTLState),
.class_init = slavio_intctl_class_init,

19
hw/intc/xilinx_intc.c
View File

@ -37,9 +37,13 @@
#define R_MER 7
#define R_MAX 8
#define TYPE_XILINX_INTC "xlnx.xps-intc"
#define XILINX_INTC(obj) OBJECT_CHECK(struct xlx_pic, (obj), TYPE_XILINX_INTC)
struct xlx_pic
{
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion mmio;
qemu_irq parent_irq;
@ -153,16 +157,17 @@ static void irq_handler(void *opaque, int irq, int level)
update_irq(p);
}
static int xilinx_intc_init(SysBusDevice *dev)
static int xilinx_intc_init(SysBusDevice *sbd)
{
struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
DeviceState *dev = DEVICE(sbd);
struct xlx_pic *p = XILINX_INTC(dev);
qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
sysbus_init_irq(dev, &p->parent_irq);
qdev_init_gpio_in(dev, irq_handler, 32);
sysbus_init_irq(sbd, &p->parent_irq);
memory_region_init_io(&p->mmio, OBJECT(p), &pic_ops, p, "xlnx.xps-intc",
R_MAX * 4);
sysbus_init_mmio(dev, &p->mmio);
sysbus_init_mmio(sbd, &p->mmio);
return 0;
}
@ -181,7 +186,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo xilinx_intc_info = {
.name = "xlnx.xps-intc",
.name = TYPE_XILINX_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct xlx_pic),
.class_init = xilinx_intc_class_init,

5
hw/lm32/lm32.h
View File

@ -1,8 +1,7 @@
#ifndef HW_LM32_H
#define HW_LM32_H 1
#include "qemu-common.h"
#include "hw/char/lm32_juart.h"
static inline DeviceState *lm32_pic_init(qemu_irq cpu_irq)
{
@ -21,7 +20,7 @@ static inline DeviceState *lm32_juart_init(void)
{
DeviceState *dev;
dev = qdev_create(NULL, "lm32-juart");
dev = qdev_create(NULL, TYPE_LM32_JUART);
qdev_init_nofail(dev);
return dev;

36
hw/misc/arm_l2x0.c
View File

@ -23,8 +23,12 @@
/* L2C-310 r3p2 */
#define CACHE_ID 0x410000c8
typedef struct l2x0_state {
SysBusDevice busdev;
#define TYPE_ARM_L2X0 "l2x0"
#define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0)
typedef struct L2x0State {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t cache_type;
uint32_t ctrl;
@ -33,19 +37,19 @@ typedef struct l2x0_state {
uint32_t tag_ctrl;
uint32_t filter_start;
uint32_t filter_end;
} l2x0_state;
} L2x0State;
static const VMStateDescription vmstate_l2x0 = {
.name = "l2x0",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctrl, l2x0_state),
VMSTATE_UINT32(aux_ctrl, l2x0_state),
VMSTATE_UINT32(data_ctrl, l2x0_state),
VMSTATE_UINT32(tag_ctrl, l2x0_state),
VMSTATE_UINT32(filter_start, l2x0_state),
VMSTATE_UINT32(filter_end, l2x0_state),
VMSTATE_UINT32(ctrl, L2x0State),
VMSTATE_UINT32(aux_ctrl, L2x0State),
VMSTATE_UINT32(data_ctrl, L2x0State),
VMSTATE_UINT32(tag_ctrl, L2x0State),
VMSTATE_UINT32(filter_start, L2x0State),
VMSTATE_UINT32(filter_end, L2x0State),
VMSTATE_END_OF_LIST()
}
};
@ -55,7 +59,7 @@ static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t cache_data;
l2x0_state *s = (l2x0_state *)opaque;
L2x0State *s = (L2x0State *)opaque;
offset &= 0xfff;
if (offset >= 0x730 && offset < 0x800) {
return 0; /* cache ops complete */
@ -97,7 +101,7 @@ static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
static void l2x0_priv_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
l2x0_state *s = (l2x0_state *)opaque;
L2x0State *s = (L2x0State *)opaque;
offset &= 0xfff;
if (offset >= 0x730 && offset < 0x800) {
/* ignore */
@ -137,7 +141,7 @@ static void l2x0_priv_write(void *opaque, hwaddr offset,
static void l2x0_priv_reset(DeviceState *dev)
{
l2x0_state *s = DO_UPCAST(l2x0_state, busdev.qdev, dev);
L2x0State *s = ARM_L2X0(dev);
s->ctrl = 0;
s->aux_ctrl = 0x02020000;
@ -155,7 +159,7 @@ static const MemoryRegionOps l2x0_mem_ops = {
static int l2x0_priv_init(SysBusDevice *dev)
{
l2x0_state *s = FROM_SYSBUS(l2x0_state, dev);
L2x0State *s = ARM_L2X0(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &l2x0_mem_ops, s,
"l2x0_cc", 0x1000);
@ -164,7 +168,7 @@ static int l2x0_priv_init(SysBusDevice *dev)
}
static Property l2x0_properties[] = {
DEFINE_PROP_UINT32("cache-type", l2x0_state, cache_type, 0x1c100100),
DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
DEFINE_PROP_END_OF_LIST(),
};
@ -181,9 +185,9 @@ static void l2x0_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo l2x0_info = {
.name = "l2x0",
.name = TYPE_ARM_L2X0,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(l2x0_state),
.instance_size = sizeof(L2x0State),
.class_init = l2x0_class_init,
};

20
hw/misc/arm_sysctl.c
View File

@ -16,8 +16,13 @@
#define LOCK_VALUE 0xa05f
#define TYPE_ARM_SYSCTL "realview_sysctl"
#define ARM_SYSCTL(obj) \
OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq pl110_mux_ctrl;
@ -85,7 +90,7 @@ static int board_id(arm_sysctl_state *s)
static void arm_sysctl_reset(DeviceState *d)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
arm_sysctl_state *s = ARM_SYSCTL(d);
int i;
s->leds = 0;
@ -587,7 +592,7 @@ static void arm_sysctl_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd);
arm_sysctl_state *s = ARM_SYSCTL(obj);
memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s,
"arm-sysctl", 0x1000);
@ -598,14 +603,15 @@ static void arm_sysctl_init(Object *obj)
static void arm_sysctl_realize(DeviceState *d, Error **errp)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
arm_sysctl_state *s = ARM_SYSCTL(d);
s->db_clock = g_new0(uint32_t, s->db_num_clocks);
}
static void arm_sysctl_finalize(Object *obj)
{
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
arm_sysctl_state *s = ARM_SYSCTL(obj);
g_free(s->db_voltage);
g_free(s->db_clock);
g_free(s->db_clock_reset);
@ -634,7 +640,7 @@ static void arm_sysctl_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo arm_sysctl_info = {
.name = "realview_sysctl",
.name = TYPE_ARM_SYSCTL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(arm_sysctl_state),
.instance_init = arm_sysctl_init,

17
hw/misc/eccmemctl.c
View File

@ -120,8 +120,12 @@
#define ECC_DIAG_SIZE 4
#define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
#define TYPE_ECC_MEMCTL "eccmemctl"
#define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL)
typedef struct ECCState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem, iomem_diag;
qemu_irq irq;
uint32_t regs[ECC_NREGS];
@ -273,13 +277,14 @@ static const VMStateDescription vmstate_ecc = {
static void ecc_reset(DeviceState *d)
{
ECCState *s = container_of(d, ECCState, busdev.qdev);
ECCState *s = ECC_MEMCTL(d);
if (s->version == ECC_MCC)
if (s->version == ECC_MCC) {
s->regs[ECC_MER] &= ECC_MER_REU;
else
} else {
s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
ECC_MER_DCI);
}
s->regs[ECC_MDR] = 0x20;
s->regs[ECC_MFSR] = 0;
s->regs[ECC_VCR] = 0;
@ -292,7 +297,7 @@ static void ecc_reset(DeviceState *d)
static int ecc_init1(SysBusDevice *dev)
{
ECCState *s = FROM_SYSBUS(ECCState, dev);
ECCState *s = ECC_MEMCTL(dev);
sysbus_init_irq(dev, &s->irq);
s->regs[0] = s->version;
@ -325,7 +330,7 @@ static void ecc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo ecc_info = {
.name = "eccmemctl",
.name = TYPE_ECC_MEMCTL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ECCState),
.class_init = ecc_class_init,

14
hw/misc/exynos4210_pmu.c
View File

@ -386,8 +386,13 @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
#define PMU_NUM_OF_REGISTERS \
(sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg))
#define TYPE_EXYNOS4210_PMU "exynos4210.pmu"
#define EXYNOS4210_PMU(obj) \
OBJECT_CHECK(Exynos4210PmuState, (obj), TYPE_EXYNOS4210_PMU)
typedef struct Exynos4210PmuState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t reg[PMU_NUM_OF_REGISTERS];
} Exynos4210PmuState;
@ -443,8 +448,7 @@ static const MemoryRegionOps exynos4210_pmu_ops = {
static void exynos4210_pmu_reset(DeviceState *dev)
{
Exynos4210PmuState *s =
container_of(dev, Exynos4210PmuState, busdev.qdev);
Exynos4210PmuState *s = EXYNOS4210_PMU(dev);
unsigned i;
/* Set default values for registers */
@ -455,7 +459,7 @@ static void exynos4210_pmu_reset(DeviceState *dev)
static int exynos4210_pmu_init(SysBusDevice *dev)
{
Exynos4210PmuState *s = FROM_SYSBUS(Exynos4210PmuState, dev);
Exynos4210PmuState *s = EXYNOS4210_PMU(dev);
/* memory mapping */
memory_region_init_io(&s->iomem, OBJECT(dev), &exynos4210_pmu_ops, s,
@ -485,7 +489,7 @@ static void exynos4210_pmu_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo exynos4210_pmu_info = {
.name = "exynos4210.pmu",
.name = TYPE_EXYNOS4210_PMU,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210PmuState),
.class_init = exynos4210_pmu_class_init,

16
hw/misc/imx_ccm.c
View File

@ -29,8 +29,12 @@ do { printf("imx_ccm: " fmt , ##args); } while (0)
static int imx_ccm_post_load(void *opaque, int version_id);
typedef struct {
SysBusDevice busdev;
#define TYPE_IMX_CCM "imx_ccm"
#define IMX_CCM(obj) OBJECT_CHECK(IMXCCMState, (obj), TYPE_IMX_CCM)
typedef struct IMXCCMState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t ccmr;
@ -108,7 +112,7 @@ static const VMStateDescription vmstate_imx_ccm = {
uint32_t imx_clock_frequency(DeviceState *dev, IMXClk clock)
{
IMXCCMState *s = container_of(dev, IMXCCMState, busdev.qdev);
IMXCCMState *s = IMX_CCM(dev);
switch (clock) {
case NOCLK:
@ -178,7 +182,7 @@ static void update_clocks(IMXCCMState *s)
static void imx_ccm_reset(DeviceState *dev)
{
IMXCCMState *s = container_of(dev, IMXCCMState, busdev.qdev);
IMXCCMState *s = IMX_CCM(dev);
s->ccmr = 0x074b0b7b;
s->pdr0 = 0xff870b48;
@ -279,7 +283,7 @@ static const struct MemoryRegionOps imx_ccm_ops = {
static int imx_ccm_init(SysBusDevice *dev)
{
IMXCCMState *s = FROM_SYSBUS(typeof(*s), dev);
IMXCCMState *s = IMX_CCM(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &imx_ccm_ops, s,
"imx_ccm", 0x1000);
@ -308,7 +312,7 @@ static void imx_ccm_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo imx_ccm_info = {
.name = "imx_ccm",
.name = TYPE_IMX_CCM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMXCCMState),
.class_init = imx_ccm_class_init,

12
hw/misc/lm32_sys.c
View File

@ -44,8 +44,12 @@ enum {
#define MAX_TESTNAME_LEN 16
#define TYPE_LM32_SYS "lm32-sys"
#define LM32_SYS(obj) OBJECT_CHECK(LM32SysState, (obj), TYPE_LM32_SYS)
struct LM32SysState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t base;
uint32_t regs[R_MAX];
@ -104,7 +108,7 @@ static const MemoryRegionOps sys_ops = {
static void sys_reset(DeviceState *d)
{
LM32SysState *s = container_of(d, LM32SysState, busdev.qdev);
LM32SysState *s = LM32_SYS(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -115,7 +119,7 @@ static void sys_reset(DeviceState *d)
static int lm32_sys_init(SysBusDevice *dev)
{
LM32SysState *s = FROM_SYSBUS(typeof(*s), dev);
LM32SysState *s = LM32_SYS(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &sys_ops , s,
"sys", R_MAX * 4);
@ -158,7 +162,7 @@ static void lm32_sys_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo lm32_sys_info = {
.name = "lm32-sys",
.name = TYPE_LM32_SYS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LM32SysState),
.class_init = lm32_sys_class_init,

13
hw/misc/milkymist-hpdmc.c
View File

@ -40,8 +40,13 @@ enum {
IODELAY_PLL2_LOCKED = (1<<7),
};
#define TYPE_MILKYMIST_HPDMC "milkymist-hpdmc"
#define MILKYMIST_HPDMC(obj) \
OBJECT_CHECK(MilkymistHpdmcState, (obj), TYPE_MILKYMIST_HPDMC)
struct MilkymistHpdmcState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion regs_region;
uint32_t regs[R_MAX];
@ -111,7 +116,7 @@ static const MemoryRegionOps hpdmc_mmio_ops = {
static void milkymist_hpdmc_reset(DeviceState *d)
{
MilkymistHpdmcState *s = container_of(d, MilkymistHpdmcState, busdev.qdev);
MilkymistHpdmcState *s = MILKYMIST_HPDMC(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -125,7 +130,7 @@ static void milkymist_hpdmc_reset(DeviceState *d)
static int milkymist_hpdmc_init(SysBusDevice *dev)
{
MilkymistHpdmcState *s = FROM_SYSBUS(typeof(*s), dev);
MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev);
memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s,
"milkymist-hpdmc", R_MAX * 4);
@ -156,7 +161,7 @@ static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_hpdmc_info = {
.name = "milkymist-hpdmc",
.name = TYPE_MILKYMIST_HPDMC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistHpdmcState),
.class_init = milkymist_hpdmc_class_init,

13
hw/misc/milkymist-pfpu.c
View File

@ -116,8 +116,13 @@ static const char *opcode_to_str[] = {
};
#endif
#define TYPE_MILKYMIST_PFPU "milkymist-pfpu"
#define MILKYMIST_PFPU(obj) \
OBJECT_CHECK(MilkymistPFPUState, (obj), TYPE_MILKYMIST_PFPU)
struct MilkymistPFPUState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion regs_region;
CharDriverState *chr;
qemu_irq irq;
@ -473,7 +478,7 @@ static const MemoryRegionOps pfpu_mmio_ops = {
static void milkymist_pfpu_reset(DeviceState *d)
{
MilkymistPFPUState *s = container_of(d, MilkymistPFPUState, busdev.qdev);
MilkymistPFPUState *s = MILKYMIST_PFPU(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -493,7 +498,7 @@ static void milkymist_pfpu_reset(DeviceState *d)
static int milkymist_pfpu_init(SysBusDevice *dev)
{
MilkymistPFPUState *s = FROM_SYSBUS(typeof(*s), dev);
MilkymistPFPUState *s = MILKYMIST_PFPU(dev);
sysbus_init_irq(dev, &s->irq);
@ -530,7 +535,7 @@ static void milkymist_pfpu_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_pfpu_info = {
.name = "milkymist-pfpu",
.name = TYPE_MILKYMIST_PFPU,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistPFPUState),
.class_init = milkymist_pfpu_class_init,

64
hw/misc/mst_fpga.c
View File

@ -35,25 +35,30 @@
#define MST_PCMCIA_CD0_IRQ 9
#define MST_PCMCIA_CD1_IRQ 13
#define TYPE_MAINSTONE_FPGA "mainstone-fpga"
#define MAINSTONE_FPGA(obj) \
OBJECT_CHECK(mst_irq_state, (obj), TYPE_MAINSTONE_FPGA)
typedef struct mst_irq_state{
SysBusDevice busdev;
MemoryRegion iomem;
SysBusDevice parent_obj;
qemu_irq parent;
MemoryRegion iomem;
uint32_t prev_level;
uint32_t leddat1;
uint32_t leddat2;
uint32_t ledctrl;
uint32_t gpswr;
uint32_t mscwr1;
uint32_t mscwr2;
uint32_t mscwr3;
uint32_t mscrd;
uint32_t intmskena;
uint32_t intsetclr;
uint32_t pcmcia0;
uint32_t pcmcia1;
qemu_irq parent;
uint32_t prev_level;
uint32_t leddat1;
uint32_t leddat2;
uint32_t ledctrl;
uint32_t gpswr;
uint32_t mscwr1;
uint32_t mscwr2;
uint32_t mscwr3;
uint32_t mscrd;
uint32_t intmskena;
uint32_t intsetclr;
uint32_t pcmcia0;
uint32_t pcmcia1;
}mst_irq_state;
static void
@ -194,24 +199,23 @@ static int mst_fpga_post_load(void *opaque, int version_id)
return 0;
}
static int mst_fpga_init(SysBusDevice *dev)
static int mst_fpga_init(SysBusDevice *sbd)
{
mst_irq_state *s;
DeviceState *dev = DEVICE(sbd);
mst_irq_state *s = MAINSTONE_FPGA(dev);
s = FROM_SYSBUS(mst_irq_state, dev);
s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
sysbus_init_irq(sbd, &s->parent);
sysbus_init_irq(dev, &s->parent);
/* alloc the external 16 irqs */
qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS);
/* alloc the external 16 irqs */
qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
"fpga", 0x00100000);
sysbus_init_mmio(dev, &s->iomem);
return 0;
memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
"fpga", 0x00100000);
sysbus_init_mmio(sbd, &s->iomem);
return 0;
}
static VMStateDescription vmstate_mst_fpga_regs = {
@ -249,7 +253,7 @@ static void mst_fpga_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mst_fpga_info = {
.name = "mainstone-fpga",
.name = TYPE_MAINSTONE_FPGA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mst_irq_state),
.class_init = mst_fpga_class_init,

12
hw/misc/puv3_pm.c
View File

@ -14,8 +14,12 @@
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
typedef struct {
SysBusDevice busdev;
#define TYPE_PUV3_PM "puv3_pm"
#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
typedef struct PUV3PMState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint32_t reg_PMCR;
@ -116,7 +120,7 @@ static const MemoryRegionOps puv3_pm_ops = {
static int puv3_pm_init(SysBusDevice *dev)
{
PUV3PMState *s = FROM_SYSBUS(PUV3PMState, dev);
PUV3PMState *s = PUV3_PM(dev);
s->reg_PCGR = 0x0;
@ -135,7 +139,7 @@ static void puv3_pm_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo puv3_pm_info = {
.name = "puv3_pm",
.name = TYPE_PUV3_PM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PUV3PMState),
.class_init = puv3_pm_class_init,

45
hw/misc/slavio_misc.c
View File

@ -34,8 +34,12 @@
* This also includes the PMC CPU idle controller.
*/
#define TYPE_SLAVIO_MISC "slavio_misc"
#define SLAVIO_MISC(obj) OBJECT_CHECK(MiscState, (obj), TYPE_SLAVIO_MISC)
typedef struct MiscState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion cfg_iomem;
MemoryRegion diag_iomem;
MemoryRegion mdm_iomem;
@ -53,8 +57,12 @@ typedef struct MiscState {
uint16_t leds;
} MiscState;
#define TYPE_APC "apc"
#define APC(obj) OBJECT_CHECK(APCState, (obj), TYPE_APC)
typedef struct APCState {
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq cpu_halt;
} APCState;
@ -88,7 +96,7 @@ static void slavio_misc_update_irq(void *opaque)
static void slavio_misc_reset(DeviceState *d)
{
MiscState *s = container_of(d, MiscState, busdev.qdev);
MiscState *s = SLAVIO_MISC(d);
// Diagnostic and system control registers not cleared in reset
s->config = s->aux1 = s->aux2 = s->mctrl = 0;
@ -407,7 +415,7 @@ static const VMStateDescription vmstate_misc = {
static int apc_init1(SysBusDevice *dev)
{
APCState *s = FROM_SYSBUS(APCState, dev);
APCState *s = APC(dev);
sysbus_init_irq(dev, &s->cpu_halt);
@ -418,52 +426,53 @@ static int apc_init1(SysBusDevice *dev)
return 0;
}
static int slavio_misc_init1(SysBusDevice *dev)
static int slavio_misc_init1(SysBusDevice *sbd)
{
MiscState *s = FROM_SYSBUS(MiscState, dev);
DeviceState *dev = DEVICE(sbd);
MiscState *s = SLAVIO_MISC(dev);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->fdc_tc);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->fdc_tc);
/* 8 bit registers */
/* Slavio control */
memory_region_init_io(&s->cfg_iomem, OBJECT(s), &slavio_cfg_mem_ops, s,
"configuration", MISC_SIZE);
sysbus_init_mmio(dev, &s->cfg_iomem);
sysbus_init_mmio(sbd, &s->cfg_iomem);
/* Diagnostics */
memory_region_init_io(&s->diag_iomem, OBJECT(s), &slavio_diag_mem_ops, s,
"diagnostic", MISC_SIZE);
sysbus_init_mmio(dev, &s->diag_iomem);
sysbus_init_mmio(sbd, &s->diag_iomem);
/* Modem control */
memory_region_init_io(&s->mdm_iomem, OBJECT(s), &slavio_mdm_mem_ops, s,
"modem", MISC_SIZE);
sysbus_init_mmio(dev, &s->mdm_iomem);
sysbus_init_mmio(sbd, &s->mdm_iomem);
/* 16 bit registers */
/* ss600mp diag LEDs */
memory_region_init_io(&s->led_iomem, OBJECT(s), &slavio_led_mem_ops, s,
"leds", MISC_SIZE);
sysbus_init_mmio(dev, &s->led_iomem);
sysbus_init_mmio(sbd, &s->led_iomem);
/* 32 bit registers */
/* System control */
memory_region_init_io(&s->sysctrl_iomem, OBJECT(s), &slavio_sysctrl_mem_ops, s,
"system-control", MISC_SIZE);
sysbus_init_mmio(dev, &s->sysctrl_iomem);
sysbus_init_mmio(sbd, &s->sysctrl_iomem);
/* AUX 1 (Misc System Functions) */
memory_region_init_io(&s->aux1_iomem, OBJECT(s), &slavio_aux1_mem_ops, s,
"misc-system-functions", MISC_SIZE);
sysbus_init_mmio(dev, &s->aux1_iomem);
sysbus_init_mmio(sbd, &s->aux1_iomem);
/* AUX 2 (Software Powerdown Control) */
memory_region_init_io(&s->aux2_iomem, OBJECT(s), &slavio_aux2_mem_ops, s,
"software-powerdown-control", MISC_SIZE);
sysbus_init_mmio(dev, &s->aux2_iomem);
sysbus_init_mmio(sbd, &s->aux2_iomem);
qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
qdev_init_gpio_in(dev, slavio_set_power_fail, 1);
return 0;
}
@ -479,7 +488,7 @@ static void slavio_misc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo slavio_misc_info = {
.name = "slavio_misc",
.name = TYPE_SLAVIO_MISC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MiscState),
.class_init = slavio_misc_class_init,
@ -493,7 +502,7 @@ static void apc_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo apc_info = {
.name = "apc",
.name = TYPE_APC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MiscState),
.class_init = apc_class_init,

15
hw/misc/zynq_slcr.c
View File

@ -114,8 +114,12 @@ typedef enum {
RESET_MAX
} ResetValues;
typedef struct {
SysBusDevice busdev;
#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
typedef struct ZynqSLCRState {
SysBusDevice parent_obj;
MemoryRegion iomem;
union {
@ -158,9 +162,8 @@ typedef struct {
static void zynq_slcr_reset(DeviceState *d)
{
ZynqSLCRState *s = ZYNQ_SLCR(d);
int i;
ZynqSLCRState *s =
FROM_SYSBUS(ZynqSLCRState, SYS_BUS_DEVICE(d));
DB_PRINT("RESET\n");
@ -492,7 +495,7 @@ static const MemoryRegionOps slcr_ops = {
static int zynq_slcr_init(SysBusDevice *dev)
{
ZynqSLCRState *s = FROM_SYSBUS(ZynqSLCRState, dev);
ZynqSLCRState *s = ZYNQ_SLCR(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &slcr_ops, s, "slcr", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
@ -523,7 +526,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, void *data)
static const TypeInfo zynq_slcr_info = {
.class_init = zynq_slcr_class_init,
.name = "xilinx,zynq_slcr",
.name = TYPE_ZYNQ_SLCR,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ZynqSLCRState),
};

26
hw/net/cadence_gem.c
View File

@ -315,8 +315,12 @@ static inline void rx_desc_set_length(unsigned *desc, unsigned len)
desc[1] |= len;
}
typedef struct {
SysBusDevice busdev;
#define TYPE_CADENCE_GEM "cadence_gem"
#define GEM(obj) OBJECT_CHECK(GemState, (obj), TYPE_CADENCE_GEM)
typedef struct GemState {
SysBusDevice parent_obj;
MemoryRegion iomem;
NICState *nic;
NICConf conf;
@ -945,7 +949,7 @@ static void gem_phy_reset(GemState *s)
static void gem_reset(DeviceState *d)
{
GemState *s = FROM_SYSBUS(GemState, SYS_BUS_DEVICE(d));
GemState *s = GEM(d);
DB_PRINT("\n");
@ -1155,22 +1159,22 @@ static NetClientInfo net_gem_info = {
.link_status_changed = gem_set_link,
};
static int gem_init(SysBusDevice *dev)
static int gem_init(SysBusDevice *sbd)
{
GemState *s;
DeviceState *dev = DEVICE(sbd);
GemState *s = GEM(dev);
DB_PRINT("\n");
s = FROM_SYSBUS(GemState, dev);
gem_init_register_masks(s);
memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
"enet", sizeof(s->regs));
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_gem_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), dev->id, s);
return 0;
}
@ -1206,10 +1210,10 @@ static void gem_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo gem_info = {
.class_init = gem_class_init,
.name = "cadence_gem",
.name = TYPE_CADENCE_GEM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(GemState),
.class_init = gem_class_init,
};
static void gem_register_types(void)

52
hw/net/etraxfs_eth.c
View File

@ -322,9 +322,14 @@ static void mdio_cycle(struct qemu_mdio *bus)
#define R_STAT 0x0b
#define FS_ETH_MAX_REGS 0x17
struct fs_eth
#define TYPE_ETRAX_FS_ETH "etraxfs-eth"
#define ETRAX_FS_ETH(obj) \
OBJECT_CHECK(ETRAXFSEthState, (obj), TYPE_ETRAX_FS_ETH)
typedef struct ETRAXFSEthState
{
SysBusDevice busdev;
SysBusDevice parent_obj;
MemoryRegion mmio;
NICState *nic;
NICConf conf;
@ -349,9 +354,9 @@ struct fs_eth
/* PHY. */
struct qemu_phy phy;
};
} ETRAXFSEthState;
static void eth_validate_duplex(struct fs_eth *eth)
static void eth_validate_duplex(ETRAXFSEthState *eth)
{
struct qemu_phy *phy;
unsigned int phy_duplex;
@ -382,7 +387,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
static uint64_t
eth_read(void *opaque, hwaddr addr, unsigned int size)
{
struct fs_eth *eth = opaque;
ETRAXFSEthState *eth = opaque;
uint32_t r = 0;
addr >>= 2;
@ -399,7 +404,7 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
return r;
}
static void eth_update_ma(struct fs_eth *eth, int ma)
static void eth_update_ma(ETRAXFSEthState *eth, int ma)
{
int reg;
int i = 0;
@ -428,7 +433,7 @@ static void
eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct fs_eth *eth = opaque;
ETRAXFSEthState *eth = opaque;
uint32_t value = val64;
addr >>= 2;
@ -472,7 +477,7 @@ eth_write(void *opaque, hwaddr addr,
/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
filter dropping group addresses we have not joined. The filter has 64
bits (m). The has function is a simple nible xor of the group addr. */
static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa)
static int eth_match_groupaddr(ETRAXFSEthState *eth, const unsigned char *sa)
{
unsigned int hsh;
int m_individual = eth->regs[RW_REC_CTRL] & 4;
@ -523,7 +528,7 @@ static int eth_can_receive(NetClientState *nc)
static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
struct fs_eth *eth = qemu_get_nic_opaque(nc);
ETRAXFSEthState *eth = qemu_get_nic_opaque(nc);
int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
int r_bcast = eth->regs[RW_REC_CTRL] & 8;
@ -547,12 +552,12 @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
/* FIXME: Find another way to pass on the fake csum. */
etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1);
return size;
return size;
}
static int eth_tx_push(void *opaque, unsigned char *buf, int len, bool eop)
{
struct fs_eth *eth = opaque;
ETRAXFSEthState *eth = opaque;
D(printf("%s buf=%p len=%d\n", __func__, buf, len));
qemu_send_packet(qemu_get_queue(eth->nic), buf, len);
@ -561,7 +566,7 @@ static int eth_tx_push(void *opaque, unsigned char *buf, int len, bool eop)
static void eth_set_link(NetClientState *nc)
{
struct fs_eth *eth = qemu_get_nic_opaque(nc);
ETRAXFSEthState *eth = qemu_get_nic_opaque(nc);
D(printf("%s %d\n", __func__, nc->link_down));
eth->phy.link = !nc->link_down;
}
@ -578,7 +583,7 @@ static const MemoryRegionOps eth_ops = {
static void eth_cleanup(NetClientState *nc)
{
struct fs_eth *eth = qemu_get_nic_opaque(nc);
ETRAXFSEthState *eth = qemu_get_nic_opaque(nc);
/* Disconnect the client. */
eth->dma_out->client.push = NULL;
@ -597,9 +602,10 @@ static NetClientInfo net_etraxfs_info = {
.link_status_changed = eth_set_link,
};
static int fs_eth_init(SysBusDevice *dev)
static int fs_eth_init(SysBusDevice *sbd)
{
struct fs_eth *s = FROM_SYSBUS(typeof(*s), dev);
DeviceState *dev = DEVICE(sbd);
ETRAXFSEthState *s = ETRAX_FS_ETH(dev);
if (!s->dma_out || !s->dma_in) {
hw_error("Unconnected ETRAX-FS Ethernet MAC.\n");
@ -612,11 +618,11 @@ static int fs_eth_init(SysBusDevice *dev)
memory_region_init_io(&s->mmio, OBJECT(dev), &eth_ops, s,
"etraxfs-eth", 0x5c);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_mmio(sbd, &s->mmio);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf,
object_get_typename(OBJECT(s)), dev->qdev.id, s);
object_get_typename(OBJECT(s)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
@ -626,10 +632,10 @@ static int fs_eth_init(SysBusDevice *dev)
}
static Property etraxfs_eth_properties[] = {
DEFINE_PROP_UINT32("phyaddr", struct fs_eth, phyaddr, 1),
DEFINE_PROP_PTR("dma_out", struct fs_eth, vdma_out),
DEFINE_PROP_PTR("dma_in", struct fs_eth, vdma_in),
DEFINE_NIC_PROPERTIES(struct fs_eth, conf),
DEFINE_PROP_UINT32("phyaddr", ETRAXFSEthState, phyaddr, 1),
DEFINE_PROP_PTR("dma_out", ETRAXFSEthState, vdma_out),
DEFINE_PROP_PTR("dma_in", ETRAXFSEthState, vdma_in),
DEFINE_NIC_PROPERTIES(ETRAXFSEthState, conf),
DEFINE_PROP_END_OF_LIST(),
};
@ -643,9 +649,9 @@ static void etraxfs_eth_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo etraxfs_eth_info = {
.name = "etraxfs-eth",
.name = TYPE_ETRAX_FS_ETH,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct fs_eth),
.instance_size = sizeof(ETRAXFSEthState),
.class_init = etraxfs_eth_class_init,
};

26
hw/net/lan9118.c
View File

@ -170,8 +170,12 @@ static const VMStateDescription vmstate_lan9118_packet = {
}
};
#define TYPE_LAN9118 "lan9118"
#define LAN9118(obj) OBJECT_CHECK(lan9118_state, (obj), TYPE_LAN9118)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
NICState *nic;
NICConf conf;
qemu_irq irq;
@ -401,7 +405,8 @@ static void phy_reset(lan9118_state *s)
static void lan9118_reset(DeviceState *d)
{
lan9118_state *s = FROM_SYSBUS(lan9118_state, SYS_BUS_DEVICE(d));
lan9118_state *s = LAN9118(d);
s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
s->int_sts = 0;
s->int_en = 0;
@ -1053,7 +1058,7 @@ static void lan9118_writel(void *opaque, hwaddr offset,
case CSR_HW_CFG:
if (val & 1) {
/* SRST */
lan9118_reset(&s->busdev.qdev);
lan9118_reset(DEVICE(s));
} else {
s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4);
}
@ -1320,9 +1325,10 @@ static NetClientInfo net_lan9118_info = {
.link_status_changed = lan9118_set_link,
};
static int lan9118_init1(SysBusDevice *dev)
static int lan9118_init1(SysBusDevice *sbd)
{
lan9118_state *s = FROM_SYSBUS(lan9118_state, dev);
DeviceState *dev = DEVICE(sbd);
lan9118_state *s = LAN9118(dev);
QEMUBH *bh;
int i;
const MemoryRegionOps *mem_ops =
@ -1330,12 +1336,12 @@ static int lan9118_init1(SysBusDevice *dev)
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
"lan9118-mmio", 0x100);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(sbd, &s->mmio);
sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
s->eeprom[0] = 0xa5;
for (i = 0; i < 6; i++) {
@ -1370,7 +1376,7 @@ static void lan9118_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo lan9118_info = {
.name = "lan9118",
.name = TYPE_LAN9118,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(lan9118_state),
.class_init = lan9118_class_init,
@ -1389,7 +1395,7 @@ void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
SysBusDevice *s;
qemu_check_nic_model(nd, "lan9118");
dev = qdev_create(NULL, "lan9118");
dev = qdev_create(NULL, TYPE_LAN9118);
qdev_set_nic_properties(dev, nd);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);

24
hw/net/lance.c
View File

@ -43,8 +43,13 @@
#include "pcnet.h"
#include "trace.h"
#define TYPE_LANCE "lance"
#define SYSBUS_PCNET(obj) \
OBJECT_CHECK(SysBusPCNetState, (obj), TYPE_LANCE)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
PCNetState state;
} SysBusPCNetState;
@ -112,28 +117,29 @@ static const VMStateDescription vmstate_lance = {
}
};
static int lance_init(SysBusDevice *dev)
static int lance_init(SysBusDevice *sbd)
{
SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
DeviceState *dev = DEVICE(sbd);
SysBusPCNetState *d = SYSBUS_PCNET(dev);
PCNetState *s = &d->state;
memory_region_init_io(&s->mmio, OBJECT(d), &lance_mem_ops, d,
"lance-mmio", 4);
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
qdev_init_gpio_in(dev, parent_lance_reset, 1);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_mmio(sbd, &s->mmio);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
s->phys_mem_read = ledma_memory_read;
s->phys_mem_write = ledma_memory_write;
return pcnet_common_init(&dev->qdev, s, &net_lance_info);
return pcnet_common_init(dev, s, &net_lance_info);
}
static void lance_reset(DeviceState *dev)
{
SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev);
SysBusPCNetState *d = SYSBUS_PCNET(dev);
pcnet_h_reset(&d->state);
}
@ -158,7 +164,7 @@ static void lance_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo lance_info = {
.name = "lance",
.name = TYPE_LANCE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SysBusPCNetState),
.class_init = lance_class_init,

27
hw/net/milkymist-minimac2.c
View File

@ -90,8 +90,13 @@ struct MilkymistMinimac2MdioState {
};
typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
#define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
#define MILKYMIST_MINIMAC2(obj) \
OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
struct MilkymistMinimac2State {
SysBusDevice busdev;
SysBusDevice parent_obj;
NICState *nic;
NICConf conf;
char *phy_model;
@ -429,8 +434,7 @@ static void minimac2_cleanup(NetClientState *nc)
static void milkymist_minimac2_reset(DeviceState *d)
{
MilkymistMinimac2State *s =
container_of(d, MilkymistMinimac2State, busdev.qdev);
MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
int i;
for (i = 0; i < R_MAX; i++) {
@ -453,17 +457,18 @@ static NetClientInfo net_milkymist_minimac2_info = {
.cleanup = minimac2_cleanup,
};
static int milkymist_minimac2_init(SysBusDevice *dev)
static int milkymist_minimac2_init(SysBusDevice *sbd)
{
MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev);
DeviceState *dev = DEVICE(sbd);
MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
sysbus_init_irq(dev, &s->rx_irq);
sysbus_init_irq(dev, &s->tx_irq);
sysbus_init_irq(sbd, &s->rx_irq);
sysbus_init_irq(sbd, &s->tx_irq);
memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
"milkymist-minimac2", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
sysbus_init_mmio(sbd, &s->regs_region);
/* register buffers memory */
memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
@ -473,11 +478,11 @@ static int milkymist_minimac2_init(SysBusDevice *dev)
s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
sysbus_init_mmio(dev, &s->buffers);
sysbus_init_mmio(sbd, &s->buffers);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
return 0;
@ -532,7 +537,7 @@ static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo milkymist_minimac2_info = {
.name = "milkymist-minimac2",
.name = TYPE_MILKYMIST_MINIMAC2,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistMinimac2State),
.class_init = milkymist_minimac2_class_init,

20
hw/net/mipsnet.c
View File

@ -19,8 +19,11 @@
#define MAX_ETH_FRAME_SIZE 1514
#define TYPE_MIPS_NET "mipsnet"
#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
typedef struct MIPSnetState {
SysBusDevice busdev;
SysBusDevice parent_obj;
uint32_t busy;
uint32_t rx_count;
@ -231,17 +234,18 @@ static const MemoryRegionOps mipsnet_ioport_ops = {
.impl.max_access_size = 4,
};
static int mipsnet_sysbus_init(SysBusDevice *dev)
static int mipsnet_sysbus_init(SysBusDevice *sbd)
{
MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev, dev);
DeviceState *dev = DEVICE(sbd);
MIPSnetState *s = MIPS_NET(dev);
memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
"mipsnet-io", 36);
sysbus_init_mmio(dev, &s->io);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(sbd, &s->io);
sysbus_init_irq(sbd, &s->irq);
s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
return 0;
@ -249,7 +253,7 @@ static int mipsnet_sysbus_init(SysBusDevice *dev)
static void mipsnet_sysbus_reset(DeviceState *dev)
{
MIPSnetState *s = DO_UPCAST(MIPSnetState, busdev.qdev, dev);
MIPSnetState *s = MIPS_NET(dev);
mipsnet_reset(s);
}
@ -272,7 +276,7 @@ static void mipsnet_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo mipsnet_info = {
.name = "mipsnet",
.name = TYPE_MIPS_NET,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MIPSnetState),
.class_init = mipsnet_class_init,

24
hw/net/opencores_eth.c
View File

@ -267,8 +267,12 @@ typedef struct desc {
#define DEFAULT_PHY 1
#define TYPE_OPEN_ETH "open_eth"
#define OPEN_ETH(obj) OBJECT_CHECK(OpenEthState, (obj), TYPE_OPEN_ETH)
typedef struct OpenEthState {
SysBusDevice dev;
SysBusDevice parent_obj;
NICState *nic;
NICConf conf;
MemoryRegion reg_io;
@ -677,28 +681,30 @@ static const MemoryRegionOps open_eth_desc_ops = {
.write = open_eth_desc_write,
};
static int sysbus_open_eth_init(SysBusDevice *dev)
static int sysbus_open_eth_init(SysBusDevice *sbd)
{
OpenEthState *s = DO_UPCAST(OpenEthState, dev, dev);
DeviceState *dev = DEVICE(sbd);
OpenEthState *s = OPEN_ETH(dev);
memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s,
"open_eth.regs", 0x54);
sysbus_init_mmio(dev, &s->reg_io);
sysbus_init_mmio(sbd, &s->reg_io);
memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s,
"open_eth.desc", 0x400);
sysbus_init_mmio(dev, &s->desc_io);
sysbus_init_mmio(sbd, &s->desc_io);
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(sbd, &s->irq);
s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
object_get_typename(OBJECT(s)), s->dev.qdev.id, s);
object_get_typename(OBJECT(s)), dev->id, s);
return 0;
}
static void qdev_open_eth_reset(DeviceState *dev)
{
OpenEthState *d = DO_UPCAST(OpenEthState, dev.qdev, dev);
OpenEthState *d = OPEN_ETH(dev);
open_eth_reset(d);
}
@ -720,7 +726,7 @@ static void open_eth_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo open_eth_info = {
.name = "open_eth",
.name = TYPE_OPEN_ETH,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OpenEthState),
.class_init = open_eth_class_init,

30
hw/net/smc91c111.c
View File

@ -16,8 +16,12 @@
/* Number of 2k memory pages available. */
#define NUM_PACKETS 4
#define TYPE_SMC91C111 "smc91c111"
#define SMC91C111(obj) OBJECT_CHECK(smc91c111_state, (obj), TYPE_SMC91C111)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
NICState *nic;
NICConf conf;
uint16_t tcr;
@ -254,7 +258,8 @@ static void smc91c111_queue_tx(smc91c111_state *s, int packet)
static void smc91c111_reset(DeviceState *dev)
{
smc91c111_state *s = FROM_SYSBUS(smc91c111_state, SYS_BUS_DEVICE(dev));
smc91c111_state *s = SMC91C111(dev);
s->bank = 0;
s->tx_fifo_len = 0;
s->tx_fifo_done_len = 0;
@ -302,8 +307,9 @@ static void smc91c111_writeb(void *opaque, hwaddr offset,
return;
case 5:
SET_HIGH(rcr, value);
if (s->rcr & RCR_SOFT_RST)
smc91c111_reset(&s->busdev.qdev);
if (s->rcr & RCR_SOFT_RST) {
smc91c111_reset(DEVICE(s));
}
return;
case 10: case 11: /* RPCR */
/* Ignored */
@ -744,16 +750,18 @@ static NetClientInfo net_smc91c111_info = {
.cleanup = smc91c111_cleanup,
};
static int smc91c111_init1(SysBusDevice *dev)
static int smc91c111_init1(SysBusDevice *sbd)
{
smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev);
DeviceState *dev = DEVICE(sbd);
smc91c111_state *s = SMC91C111(dev);
memory_region_init_io(&s->mmio, OBJECT(s), &smc91c111_mem_ops, s,
"smc91c111-mmio", 16);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(sbd, &s->mmio);
sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
/* ??? Save/restore. */
return 0;
@ -776,7 +784,7 @@ static void smc91c111_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo smc91c111_info = {
.name = "smc91c111",
.name = TYPE_SMC91C111,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(smc91c111_state),
.class_init = smc91c111_class_init,
@ -795,7 +803,7 @@ void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
SysBusDevice *s;
qemu_check_nic_model(nd, "smc91c111");
dev = qdev_create(NULL, "smc91c111");
dev = qdev_create(NULL, TYPE_SMC91C111);
qdev_set_nic_properties(dev, nd);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);

38
hw/net/stellaris_enet.c
View File

@ -42,8 +42,13 @@ do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
#define SE_TCTL_CRC 0x04
#define SE_TCTL_DUPLEX 0x08
#define TYPE_STELLARIS_ENET "stellaris_enet"
#define STELLARIS_ENET(obj) \
OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET)
typedef struct {
SysBusDevice busdev;
SysBusDevice parent_obj;
uint32_t ris;
uint32_t im;
uint32_t rctl;
@ -386,11 +391,7 @@ static void stellaris_enet_cleanup(NetClientState *nc)
{
stellaris_enet_state *s = qemu_get_nic_opaque(nc);
unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
memory_region_destroy(&s->mmio);
g_free(s);
s->nic = NULL;
}
static NetClientInfo net_stellaris_enet_info = {
@ -401,26 +402,36 @@ static NetClientInfo net_stellaris_enet_info = {
.cleanup = stellaris_enet_cleanup,
};
static int stellaris_enet_init(SysBusDevice *dev)
static int stellaris_enet_init(SysBusDevice *sbd)
{
stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
DeviceState *dev = DEVICE(sbd);
stellaris_enet_state *s = STELLARIS_ENET(dev);
memory_region_init_io(&s->mmio, OBJECT(s), &stellaris_enet_ops, s,
"stellaris_enet", 0x1000);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
sysbus_init_mmio(sbd, &s->mmio);
sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
object_get_typename(OBJECT(dev)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
stellaris_enet_reset(s);
register_savevm(&s->busdev.qdev, "stellaris_enet", -1, 1,
register_savevm(dev, "stellaris_enet", -1, 1,
stellaris_enet_save, stellaris_enet_load, s);
return 0;
}
static void stellaris_enet_unrealize(DeviceState *dev, Error **errp)
{
stellaris_enet_state *s = STELLARIS_ENET(dev);
unregister_savevm(DEVICE(s), "stellaris_enet", s);
memory_region_destroy(&s->mmio);
}
static Property stellaris_enet_properties[] = {
DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
DEFINE_PROP_END_OF_LIST(),
@ -432,11 +443,12 @@ static void stellaris_enet_class_init(ObjectClass *klass, void *data)
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = stellaris_enet_init;
dc->unrealize = stellaris_enet_unrealize;
dc->props = stellaris_enet_properties;
}
static const TypeInfo stellaris_enet_info = {
.name = "stellaris_enet",
.name = TYPE_STELLARIS_ENET,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(stellaris_enet_state),
.class_init = stellaris_enet_class_init,

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