mirror of https://gitee.com/openkylin/qemu.git
target/arm: Implement ARMv8.3-JSConv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed a couple of comment typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
e80941bd64
commit
6c1f6f2733
|
|
@ -2001,6 +2001,7 @@ static void arm_max_initfn(Object *obj)
|
|||
cpu->isar.id_isar5 = t;
|
||||
|
||||
t = cpu->isar.id_isar6;
|
||||
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
|
||||
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
|
||||
cpu->isar.id_isar6 = t;
|
||||
|
||||
|
|
|
|||
|
|
@ -3273,6 +3273,11 @@ static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
|
|||
return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
|
||||
{
|
||||
return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
|
||||
{
|
||||
return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
|
||||
|
|
@ -3351,6 +3356,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
|
|||
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
|
||||
{
|
||||
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
|
||||
}
|
||||
|
||||
static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
|
||||
{
|
||||
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
|
||||
|
|
|
|||
|
|
@ -311,6 +311,7 @@ static void aarch64_max_initfn(Object *obj)
|
|||
cpu->isar.id_aa64isar0 = t;
|
||||
|
||||
t = cpu->isar.id_aa64isar1;
|
||||
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
|
||||
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
|
||||
t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
|
||||
t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
|
||||
|
|
@ -344,6 +345,7 @@ static void aarch64_max_initfn(Object *obj)
|
|||
cpu->isar.id_isar5 = u;
|
||||
|
||||
u = cpu->isar.id_isar6;
|
||||
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
|
||||
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
|
||||
cpu->isar.id_isar6 = u;
|
||||
|
||||
|
|
|
|||
|
|
@ -218,6 +218,9 @@ DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr)
|
|||
DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr)
|
||||
DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
|
||||
DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr)
|
||||
|
||||
/* neon_helper.c */
|
||||
DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
|
||||
|
|
|
|||
|
|
@ -6526,6 +6526,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
|
|||
}
|
||||
}
|
||||
|
||||
static void handle_fjcvtzs(DisasContext *s, int rd, int rn)
|
||||
{
|
||||
TCGv_i64 t = read_fp_dreg(s, rn);
|
||||
TCGv_ptr fpstatus = get_fpstatus_ptr(false);
|
||||
|
||||
gen_helper_fjcvtzs(t, t, fpstatus);
|
||||
|
||||
tcg_temp_free_ptr(fpstatus);
|
||||
|
||||
tcg_gen_ext32u_i64(cpu_reg(s, rd), t);
|
||||
tcg_gen_extrh_i64_i32(cpu_ZF, t);
|
||||
tcg_gen_movi_i32(cpu_CF, 0);
|
||||
tcg_gen_movi_i32(cpu_NF, 0);
|
||||
tcg_gen_movi_i32(cpu_VF, 0);
|
||||
|
||||
tcg_temp_free_i64(t);
|
||||
}
|
||||
|
||||
/* Floating point <-> integer conversions
|
||||
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
|
||||
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
|
||||
|
|
@ -6601,6 +6619,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
|
|||
handle_fmov(s, rd, rn, type, itof);
|
||||
break;
|
||||
|
||||
case 0b00111110: /* FJCVTZS */
|
||||
if (!dc_isar_feature(aa64_jscvt, s)) {
|
||||
goto do_unallocated;
|
||||
} else if (fp_access_check(s)) {
|
||||
handle_fjcvtzs(s, rd, rn);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
do_unallocated:
|
||||
unallocated_encoding(s);
|
||||
|
|
|
|||
|
|
@ -3718,6 +3718,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
|
|||
rm_is_dp = false;
|
||||
break;
|
||||
|
||||
case 0x13: /* vjcvt */
|
||||
if (!dp || !dc_isar_feature(aa32_jscvt, s)) {
|
||||
return 1;
|
||||
}
|
||||
rd_is_dp = false;
|
||||
break;
|
||||
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -4088,6 +4095,9 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
|
|||
case 17: /* fsito */
|
||||
gen_vfp_sito(dp, 0);
|
||||
break;
|
||||
case 19: /* vjcvt */
|
||||
gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env);
|
||||
break;
|
||||
case 20: /* fshto */
|
||||
gen_vfp_shto(dp, 16 - rm, 0);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1086,3 +1086,91 @@ int arm_rmode_to_sf(int rmode)
|
|||
}
|
||||
return rmode;
|
||||
}
|
||||
|
||||
/*
|
||||
* Implement float64 to int32_t conversion without saturation;
|
||||
* the result is supplied modulo 2^32.
|
||||
*/
|
||||
uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
|
||||
{
|
||||
float_status *status = vstatus;
|
||||
uint32_t exp, sign;
|
||||
uint64_t frac;
|
||||
uint32_t inexact = 1; /* !Z */
|
||||
|
||||
sign = extract64(value, 63, 1);
|
||||
exp = extract64(value, 52, 11);
|
||||
frac = extract64(value, 0, 52);
|
||||
|
||||
if (exp == 0) {
|
||||
/* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
|
||||
inexact = sign;
|
||||
if (frac != 0) {
|
||||
if (status->flush_inputs_to_zero) {
|
||||
float_raise(float_flag_input_denormal, status);
|
||||
} else {
|
||||
float_raise(float_flag_inexact, status);
|
||||
inexact = 1;
|
||||
}
|
||||
}
|
||||
frac = 0;
|
||||
} else if (exp == 0x7ff) {
|
||||
/* This operation raises Invalid for both NaN and overflow (Inf). */
|
||||
float_raise(float_flag_invalid, status);
|
||||
frac = 0;
|
||||
} else {
|
||||
int true_exp = exp - 1023;
|
||||
int shift = true_exp - 52;
|
||||
|
||||
/* Restore implicit bit. */
|
||||
frac |= 1ull << 52;
|
||||
|
||||
/* Shift the fraction into place. */
|
||||
if (shift >= 0) {
|
||||
/* The number is so large we must shift the fraction left. */
|
||||
if (shift >= 64) {
|
||||
/* The fraction is shifted out entirely. */
|
||||
frac = 0;
|
||||
} else {
|
||||
frac <<= shift;
|
||||
}
|
||||
} else if (shift > -64) {
|
||||
/* Normal case -- shift right and notice if bits shift out. */
|
||||
inexact = (frac << (64 + shift)) != 0;
|
||||
frac >>= -shift;
|
||||
} else {
|
||||
/* The fraction is shifted out entirely. */
|
||||
frac = 0;
|
||||
}
|
||||
|
||||
/* Notice overflow or inexact exceptions. */
|
||||
if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
|
||||
/* Overflow, for which this operation raises invalid. */
|
||||
float_raise(float_flag_invalid, status);
|
||||
inexact = 1;
|
||||
} else if (inexact) {
|
||||
float_raise(float_flag_inexact, status);
|
||||
}
|
||||
|
||||
/* Honor the sign. */
|
||||
if (sign) {
|
||||
frac = -frac;
|
||||
}
|
||||
}
|
||||
|
||||
/* Pack the result and the env->ZF representation of Z together. */
|
||||
return deposit64(frac, 32, 32, inexact);
|
||||
}
|
||||
|
||||
uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
|
||||
{
|
||||
uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
|
||||
uint32_t result = pair;
|
||||
uint32_t z = (pair >> 32) == 0;
|
||||
|
||||
/* Store Z, clear NCV, in FPSCR.NZCV. */
|
||||
env->vfp.xregs[ARM_VFP_FPSCR]
|
||||
= (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue