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pnv/xive2: Introduce new capability bits 

These bits control the availability of interrupt features : StoreEOI,
PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
exploitation mode. These bits can be set at early boot time of the
system to activate/deactivate a feature for testing purposes. The
default value should be '1'.

The 'XIVE exploitation mode' bit is a software bit that skiboot could
use to disable the XIVE OS interface and propose a P8 style XICS
interface instead. There are no plans for that for the moment.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Cédric Le Goater 2022-03-02 06:51:39 +01:00
parent 34b0696be4
commit 707ea7ab4d
2 changed files with 7 additions and 2 deletions
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4
hw/intc/pnv_xive2.c
View File

@ -1709,9 +1709,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = {
};
/*
* POWER10 default capabilities: 0x2000120076f00000
* POWER10 default capabilities: 0x2000120076f000FC
*/
#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000
#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC
/*
* POWER10 default configuration: 0x0030000033000000

5
hw/intc/pnv_xive2_regs.h
View File

@ -31,6 +31,11 @@
#define CQ_XIVE_CAP_VP_INT_PRIO_8 3
#define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
/* XIVE2 Configuration */
#define X_CQ_XIVE_CFG 0x03
#define CQ_XIVE_CFG 0x018