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Fix off-by-one errors for Altivec and SPE registers 

Altivec and SPE both have 34 registers in their register sets, not 35
with a missing register 32.

GDB would ask for register 32 of the Altivec (resp. SPE) registers and
the code would claim it had zero width.  The QEMU GDB stub code would
then return an E14 to GDB, which would complain about not being sure
whether p packets were supported or not.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6769 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-03-07 22:00:49 +00:00
parent e60f469ca8
commit 70976a7926
1 changed files with 8 additions and 8 deletions
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16
target-ppc/translate_init.c
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@ -9379,11 +9379,11 @@ static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
#endif
return 16;
}
if (n == 33) {
if (n == 32) {
stl_p(mem_buf, env->vscr);
return 4;
}
if (n == 34) {
if (n == 33) {
stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
return 4;
}
@ -9402,11 +9402,11 @@ static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
#endif
return 16;
}
if (n == 33) {
if (n == 32) {
env->vscr = ldl_p(mem_buf);
return 4;
}
if (n == 34) {
if (n == 33) {
env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
return 4;
}
@ -9423,11 +9423,11 @@ static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
#endif
return 4;
}
if (n == 33) {
if (n == 32) {
stq_p(mem_buf, env->spe_acc);
return 8;
}
if (n == 34) {
if (n == 33) {
/* SPEFSCR not implemented */
memset(mem_buf, 0, 4);
return 4;
@ -9447,11 +9447,11 @@ static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
#endif
return 4;
}
if (n == 33) {
if (n == 32) {
env->spe_acc = ldq_p(mem_buf);
return 8;
}
if (n == 34) {
if (n == 33) {
/* SPEFSCR not implemented */
return 4;
}