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target-sh4: Don't overuse CPUState 

Scripted conversion:
  sed -i "s/CPUState/CPUSH4State/g" target-sh4/*.[hc]
  sed -i "s/#define CPUSH4State/#define CPUState/" target-sh4/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-03-14 01:38:22 +01:00
parent a4e3ad19d2
commit 73e5716c89
4 changed files with 44 additions and 44 deletions
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10
target-sh4/cpu.h
View File

@ -240,13 +240,13 @@ void cpu_load_tlb(CPUSH4State * env);
#define MMU_MODE0_SUFFIX _kernel #define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user #define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1 #define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env) static inline int cpu_mmu_index (CPUSH4State *env)
{ {
return (env->sr & SR_MD) == 0 ? 1 : 0; return (env->sr & SR_MD) == 0 ? 1 : 0;
} }
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp)
{ {
if (newsp) if (newsp)
env->gregs[15] = newsp; env->gregs[15] = newsp;
@ -348,7 +348,7 @@ static inline int cpu_ptel_pr (uint32_t ptel)
#define TB_FLAG_PENDING_MOVCA (1 << 4) #define TB_FLAG_PENDING_MOVCA (1 << 4)
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
target_ulong *cs_base, int *flags) target_ulong *cs_base, int *flags)
{ {
*pc = env->pc; *pc = env->pc;
@ -361,14 +361,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
} }
static inline bool cpu_has_work(CPUState *env) static inline bool cpu_has_work(CPUSH4State *env)
{ {
return env->interrupt_request & CPU_INTERRUPT_HARD; return env->interrupt_request & CPU_INTERRUPT_HARD;
} }
#include "exec-all.h" #include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb)
{ {
env->pc = tb->pc; env->pc = tb->pc;
env->flags = tb->flags; env->flags = tb->flags;

28
target-sh4/helper.c
View File

@ -31,12 +31,12 @@
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUState *env) void do_interrupt (CPUSH4State *env)
{ {
env->exception_index = -1; env->exception_index = -1;
} }
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
int mmu_idx) int mmu_idx)
{ {
env->tea = address; env->tea = address;
@ -78,7 +78,7 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
#define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_READ (-12)
#define MMU_DADDR_ERROR_WRITE (-13) #define MMU_DADDR_ERROR_WRITE (-13)
void do_interrupt(CPUState * env) void do_interrupt(CPUSH4State * env)
{ {
int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD; int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
int do_exp, irq_vector = env->exception_index; int do_exp, irq_vector = env->exception_index;
@ -202,7 +202,7 @@ void do_interrupt(CPUState * env)
} }
} }
static void update_itlb_use(CPUState * env, int itlbnb) static void update_itlb_use(CPUSH4State * env, int itlbnb)
{ {
uint8_t or_mask = 0, and_mask = (uint8_t) - 1; uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
@ -227,7 +227,7 @@ static void update_itlb_use(CPUState * env, int itlbnb)
env->mmucr |= (or_mask << 24); env->mmucr |= (or_mask << 24);
} }
static int itlb_replacement(CPUState * env) static int itlb_replacement(CPUSH4State * env)
{ {
if ((env->mmucr & 0xe0000000) == 0xe0000000) if ((env->mmucr & 0xe0000000) == 0xe0000000)
return 0; return 0;
@ -243,7 +243,7 @@ static int itlb_replacement(CPUState * env)
/* Find the corresponding entry in the right TLB /* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/ */
static int find_tlb_entry(CPUState * env, target_ulong address, static int find_tlb_entry(CPUSH4State * env, target_ulong address,
tlb_t * entries, uint8_t nbtlb, int use_asid) tlb_t * entries, uint8_t nbtlb, int use_asid)
{ {
int match = MMU_DTLB_MISS; int match = MMU_DTLB_MISS;
@ -269,7 +269,7 @@ static int find_tlb_entry(CPUState * env, target_ulong address,
return match; return match;
} }
static void increment_urc(CPUState * env) static void increment_urc(CPUSH4State * env)
{ {
uint8_t urb, urc; uint8_t urb, urc;
@ -285,7 +285,7 @@ static void increment_urc(CPUState * env)
/* Copy and utlb entry into itlb /* Copy and utlb entry into itlb
Return entry Return entry
*/ */
static int copy_utlb_entry_itlb(CPUState *env, int utlb) static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
{ {
int itlb; int itlb;
@ -303,7 +303,7 @@ static int copy_utlb_entry_itlb(CPUState *env, int utlb)
/* Find itlb entry /* Find itlb entry
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
*/ */
static int find_itlb_entry(CPUState * env, target_ulong address, static int find_itlb_entry(CPUSH4State * env, target_ulong address,
int use_asid) int use_asid)
{ {
int e; int e;
@ -321,7 +321,7 @@ static int find_itlb_entry(CPUState * env, target_ulong address,
/* Find utlb entry /* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
{ {
/* per utlb access */ /* per utlb access */
increment_urc(env); increment_urc(env);
@ -337,7 +337,7 @@ static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION, MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE. MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/ */
static int get_mmu_address(CPUState * env, target_ulong * physical, static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address, int *prot, target_ulong address,
int rw, int access_type) int rw, int access_type)
{ {
@ -403,7 +403,7 @@ static int get_mmu_address(CPUState * env, target_ulong * physical,
return n; return n;
} }
static int get_physical_address(CPUState * env, target_ulong * physical, static int get_physical_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address, int *prot, target_ulong address,
int rw, int access_type) int rw, int access_type)
{ {
@ -442,7 +442,7 @@ static int get_physical_address(CPUState * env, target_ulong * physical,
return get_mmu_address(env, physical, prot, address, rw, access_type); return get_mmu_address(env, physical, prot, address, rw, access_type);
} }
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
int mmu_idx) int mmu_idx)
{ {
target_ulong physical; target_ulong physical;
@ -503,7 +503,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
return 0; return 0;
} }
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) target_phys_addr_t cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
{ {
target_ulong physical; target_ulong physical;
int prot; int prot;

4
target-sh4/op_helper.c
View File

@ -55,10 +55,10 @@ static void cpu_restore_state_from_retaddr(void *retaddr)
#define SHIFT 3 #define SHIFT 3
#include "softmmu_template.h" #include "softmmu_template.h"
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr) void *retaddr)
{ {
CPUState *saved_env; CPUSH4State *saved_env;
int ret; int ret;
saved_env = env; saved_env = env;

46
target-sh4/translate.c
View File

@ -103,47 +103,47 @@ static void sh4_translate_init(void)
for (i = 0; i < 24; i++) for (i = 0; i < 24; i++)
cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, gregs[i]), offsetof(CPUSH4State, gregs[i]),
gregnames[i]); gregnames[i]);
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, pc), "PC"); offsetof(CPUSH4State, pc), "PC");
cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, sr), "SR"); offsetof(CPUSH4State, sr), "SR");
cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, ssr), "SSR"); offsetof(CPUSH4State, ssr), "SSR");
cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, spc), "SPC"); offsetof(CPUSH4State, spc), "SPC");
cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, gbr), "GBR"); offsetof(CPUSH4State, gbr), "GBR");
cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, vbr), "VBR"); offsetof(CPUSH4State, vbr), "VBR");
cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, sgr), "SGR"); offsetof(CPUSH4State, sgr), "SGR");
cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, dbr), "DBR"); offsetof(CPUSH4State, dbr), "DBR");
cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, mach), "MACH"); offsetof(CPUSH4State, mach), "MACH");
cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, macl), "MACL"); offsetof(CPUSH4State, macl), "MACL");
cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, pr), "PR"); offsetof(CPUSH4State, pr), "PR");
cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, fpscr), "FPSCR"); offsetof(CPUSH4State, fpscr), "FPSCR");
cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, fpul), "FPUL"); offsetof(CPUSH4State, fpul), "FPUL");
cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, flags), "_flags_"); offsetof(CPUSH4State, flags), "_flags_");
cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, delayed_pc), offsetof(CPUSH4State, delayed_pc),
"_delayed_pc_"); "_delayed_pc_");
cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0, cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, ldst), "_ldst_"); offsetof(CPUSH4State, ldst), "_ldst_");
for (i = 0; i < 32; i++) for (i = 0; i < 32; i++)
cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, fregs[i]), offsetof(CPUSH4State, fregs[i]),
fregnames[i]); fregnames[i]);
/* register helpers */ /* register helpers */
@ -153,7 +153,7 @@ static void sh4_translate_init(void)
done_init = 1; done_init = 1;
} }
void cpu_dump_state(CPUState * env, FILE * f, void cpu_dump_state(CPUSH4State * env, FILE * f,
int (*cpu_fprintf) (FILE * f, const char *fmt, ...), int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
int flags) int flags)
{ {
@ -1918,7 +1918,7 @@ static void decode_opc(DisasContext * ctx)
} }
static inline void static inline void
gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
int search_pc) int search_pc)
{ {
DisasContext ctx; DisasContext ctx;
@ -2044,17 +2044,17 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
#endif #endif
} }
void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
{ {
gen_intermediate_code_internal(env, tb, 0); gen_intermediate_code_internal(env, tb, 0);
} }
void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb)
{ {
gen_intermediate_code_internal(env, tb, 1); gen_intermediate_code_internal(env, tb, 1);
} }
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos)
{ {
env->pc = gen_opc_pc[pc_pos]; env->pc = gen_opc_pc[pc_pos];
env->flags = gen_opc_hflags[pc_pos]; env->flags = gen_opc_hflags[pc_pos];