From d56974afe980b2bb8d60b17729483d80a7692400 Mon Sep 17 00:00:00 2001 From: Luc Michel Date: Thu, 19 Sep 2019 14:18:40 +0100 Subject: [PATCH 1/9] target/arm: fix CBAR register for AArch64 CPUs For AArch64 CPUs with a CBAR register, we have two views for it: - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the full 64 bits CBAR value - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0) returns a 32 bits view such that: CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32] This commit fixes the current implementation where: - CBAR_EL1 was returning the 32 bits view instead of the full 64 bits value, - CBAR was returning a truncated 32 bits version of the full 64 bits one, instead of the 32 bits view - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in ARMv8 CPUs. Signed-off-by: Luc Michel Message-id: 20190912110103.1417887-1-luc.michel@greensocs.com [PMM: Added a comment about the two different kinds of CBAR] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 507026c915..bc1130d989 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6733,6 +6733,19 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_CBAR)) { + /* + * CBAR is IMPDEF, but common on Arm Cortex-A implementations. + * There are two flavours: + * (1) older 32-bit only cores have a simple 32-bit CBAR + * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a + * 32-bit register visible to AArch32 at a different encoding + * to the "flavour 1" register and with the bits rearranged to + * be able to squash a 64-bit address into the 32-bit view. + * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but + * in future if we support AArch32-only configs of some of the + * AArch64 cores we might need to add a specific feature flag + * to indicate cores with "flavour 2" CBAR. + */ if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 32 bit view is [31:18] 0...0 [43:32]. */ uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) @@ -6740,12 +6753,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo cbar_reginfo[] = { { .name = "CBAR", .type = ARM_CP_CONST, - .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, - .access = PL1_R, .resetvalue = cpu->reset_cbar }, + .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, + .access = PL1_R, .resetvalue = cbar32 }, { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_CONST, .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, - .access = PL1_R, .resetvalue = cbar32 }, + .access = PL1_R, .resetvalue = cpu->reset_cbar }, REGINFO_SENTINEL }; /* We don't implement a r/w 64 bit CBAR currently */ From 72ab7f9e1d811256ceca7c1d9d79f5ff72a4e0c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 19 Sep 2019 14:18:40 +0100 Subject: [PATCH 2/9] tests/tcg: clean-up some comments after the de-tangling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Message-id: 20190913151845.12582-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/Makefile.target | 7 +++++-- tests/tcg/aarch64/Makefile.target | 3 ++- tests/tcg/arm/Makefile.target | 15 ++++++++------- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 8808beaf74..679eb56bd3 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -74,8 +74,11 @@ TIMEOUT=15 endif ifdef CONFIG_USER_ONLY -# The order we include is important. We include multiarch, base arch -# and finally arch if it's not the same as base arch. +# The order we include is important. We include multiarch first and +# then the target. If there are common tests shared between +# sub-targets (e.g. ARM & AArch64) then it is up to +# $(TARGET_NAME)/Makefile.target to include the common parent +# architecture in its VPATH. -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index e763dd9da3..9758f89f90 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,7 +8,7 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# we don't build any other ARM test +# Float-convert Tests AARCH64_TESTS=fcvt fcvt: LDFLAGS+=-lm @@ -17,6 +17,7 @@ run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) +# Pauth Tests AARCH64_TESTS += pauth-1 pauth-2 run-pauth-%: QEMU_OPTS += -cpu max diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index aa4e4e3782..7347d3d0ad 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -8,25 +8,26 @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm # Set search path for all sources VPATH += $(ARM_SRC) -ARM_TESTS=hello-arm test-arm-iwmmxt - -TESTS += $(ARM_TESTS) fcvt - +# Basic Hello World +ARM_TESTS = hello-arm hello-arm: CFLAGS+=-marm -ffreestanding hello-arm: LDFLAGS+=-nostdlib +# IWMXT floating point extensions +ARM_TESTS += test-arm-iwmmxt test-arm-iwmmxt: CFLAGS+=-marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 test-arm-iwmmxt: test-arm-iwmmxt.S $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) -ifeq ($(TARGET_NAME), arm) +# Float-convert Tests +ARM_TESTS += fcvt fcvt: LDFLAGS+=-lm # fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8 - run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) -endif + +TESTS += $(ARM_TESTS) # On ARM Linux only supports 4k pages EXTRA_RUNS+=run-test-mmap-4096 From 376214e4f499f82900e699c225f18f045f8a3c20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 19 Sep 2019 14:18:40 +0100 Subject: [PATCH 3/9] target/arm: handle M-profile semihosting at translate time MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We do this for other semihosting calls so we might as well do it for M-profile as well. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20190913151845.12582-3-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/m_helper.c | 18 ++++++------------ target/arm/translate.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 884d35d2b0..27cd2f3f96 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2114,19 +2114,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; } break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] = do_arm_semihosting(env); + return; case EXCP_BKPT: - if (semihosting_enabled()) { - int nr; - nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; - if (nr == 0xab) { - env->regs[15] += 2; - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] = do_arm_semihosting(env); - return; - } - } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 34bb280e3d..b527211933 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8424,7 +8424,16 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) if (!ENABLE_ARCH_5) { return false; } - gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + if (arm_dc_feature(s, ARM_FEATURE_M) && + semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + !IS_USER(s) && +#endif + (a->imm == 0xab)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + } return true; } From 5651697f1f405a023378cbd35e3528788fed2166 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 19 Sep 2019 14:18:40 +0100 Subject: [PATCH 4/9] target/arm: handle A-profile semihosting at translate time MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Message-id: 20190913151845.12582-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b527211933..698c594e8c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10222,14 +10222,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) } /* - * Supervisor call + * Supervisor call - both T32 & A32 come here so we need to check + * which mode we are in when checking for semihosting. */ static bool trans_SVC(DisasContext *s, arg_SVC *a) { - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = a->imm; - s->base.is_jmp = DISAS_SWI; + const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456; + + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + !IS_USER(s) && +#endif + (a->imm == semihost_imm)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = a->imm; + s->base.is_jmp = DISAS_SWI; + } return true; } From ed6e6ba9c4c0539e4f9ef534bc88d487262a9063 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 19 Sep 2019 14:18:41 +0100 Subject: [PATCH 5/9] target/arm: remove run time semihosting checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now we do all our checking and use a common EXCP_SEMIHOST for semihosting operations we can make helper code a lot simpler. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20190913151845.12582-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 96 +++++++++++---------------------------------- 1 file changed, 22 insertions(+), 74 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bc1130d989..0d9a2d2ab7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8352,88 +8352,32 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) new_el, env->pc, pstate_read(env)); } -static inline bool check_for_semihosting(CPUState *cs) -{ +/* + * Do semihosting call and set the appropriate return value. All the + * permission and validity checks have been done at translate time. + * + * We only see semihosting exceptions in TCG only as they are not + * trapped to the hypervisor in KVM. + */ #ifdef CONFIG_TCG - /* Check whether this exception is a semihosting call; if so - * then handle it and return true; otherwise return false. - */ +static void handle_semihosting(CPUState *cs) +{ ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; if (is_a64(env)) { - if (cs->exception_index == EXCP_SEMIHOST) { - /* This is always the 64-bit semihosting exception. - * The "is this usermode" and "is semihosting enabled" - * checks have been done at translate time. - */ - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n", - env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); - return true; - } - return false; + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] = do_arm_semihosting(env); } else { - uint32_t imm; - - /* Only intercept calls from privileged modes, to provide some - * semblance of security. - */ - if (cs->exception_index != EXCP_SEMIHOST && - (!semihosting_enabled() || - ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { - return false; - } - - switch (cs->exception_index) { - case EXCP_SEMIHOST: - /* This is always a semihosting call; the "is this usermode" - * and "is semihosting enabled" checks have been done at - * translate time. - */ - break; - case EXCP_SWI: - /* Check for semihosting interrupt. */ - if (env->thumb) { - imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) - & 0xff; - if (imm == 0xab) { - break; - } - } else { - imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) - & 0xffffff; - if (imm == 0x123456) { - break; - } - } - return false; - case EXCP_BKPT: - /* See if this is a semihosting syscall. */ - if (env->thumb) { - imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) - & 0xff; - if (imm == 0xab) { - env->regs[15] += 2; - break; - } - } - return false; - default: - return false; - } - qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] = do_arm_semihosting(env); - return true; } -#else - return false; -#endif } +#endif /* Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off @@ -8464,13 +8408,17 @@ void arm_cpu_do_interrupt(CPUState *cs) return; } - /* Semihosting semantics depend on the register width of the - * code that caused the exception, not the target exception level, - * so must be handled here. + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. */ - if (check_for_semihosting(cs)) { +#ifdef CONFIG_TCG + if (cs->exception_index == EXCP_SEMIHOST) { + handle_semihosting(cs); return; } +#endif /* Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of From e267255957fc82db47f96da1ff56409093b824e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 19 Sep 2019 14:18:41 +0100 Subject: [PATCH 6/9] target/arm: remove run-time semihosting checks for linux-user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now we do all our checking at translate time we can make cpu_loop a little bit simpler. We also introduce a simple linux-user semihosting test case to defend the functionality. The out-of-tree softmmu based semihosting tests are still more comprehensive. Signed-off-by: Alex Bennée Message-id: 20190913151845.12582-6-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- linux-user/arm/cpu_loop.c | 3 --- linux-user/arm/target_syscall.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 8d65de5b9f..e28c45cd4a 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -325,9 +325,6 @@ void cpu_loop(CPUARMState *env) if (n == ARM_NR_cacheflush) { /* nop */ - } else if (n == ARM_NR_semihosting - || n == ARM_NR_thumb_semihosting) { - env->regs[0] = do_arm_semihosting (env); } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { /* linux syscall */ if (env->thumb || n == 0) { diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h index afc0772e19..f85cbdaf56 100644 --- a/linux-user/arm/target_syscall.h +++ b/linux-user/arm/target_syscall.h @@ -18,9 +18,6 @@ struct target_pt_regs { #define ARM_NR_set_tls (ARM_NR_BASE + 5) #define ARM_NR_get_tls (ARM_NR_BASE + 6) -#define ARM_NR_semihosting 0x123456 -#define ARM_NR_thumb_semihosting 0xAB - #if defined(TARGET_WORDS_BIGENDIAN) #define UNAME_MACHINE "armv5teb" #else From 83704ceff1b81b750f50464643084aa7cc5608fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 19 Sep 2019 14:18:41 +0100 Subject: [PATCH 7/9] tests/tcg: add linux-user semihosting smoke test for ARM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We already use semihosting for the system stuff so this is a simple smoke test to ensure we are working OK on linux-user. Signed-off-by: Alex Bennée Message-id: 20190913151845.12582-7-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/tcg/aarch64/Makefile.target | 5 ++++ tests/tcg/arm/Makefile.target | 5 ++++ tests/tcg/arm/semihosting.c | 45 +++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100644 tests/tcg/arm/semihosting.c diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 9758f89f90..509f1afa93 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -21,4 +21,9 @@ run-fcvt: fcvt AARCH64_TESTS += pauth-1 pauth-2 run-pauth-%: QEMU_OPTS += -cpu max +# Semihosting smoke test for linux-user +AARCH64_TESTS += semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS += $(AARCH64_TESTS) diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 7347d3d0ad..3b7fc9a64b 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -27,6 +27,11 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# Semihosting smoke test for linux-user +ARM_TESTS += semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS += $(ARM_TESTS) # On ARM Linux only supports 4k pages diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c new file mode 100644 index 0000000000..09c89cb481 --- /dev/null +++ b/tests/tcg/arm/semihosting.c @@ -0,0 +1,45 @@ +/* + * linux-user semihosting checks + * + * Copyright (c) 2019 + * Written by Alex Bennée + * + * SPDX-License-Identifier: GPL-3.0-or-later + */ + +#include + +#define SYS_WRITE0 0x04 +#define SYS_REPORTEXC 0x18 + +void __semi_call(uintptr_t type, uintptr_t arg0) +{ +#if defined(__arm__) + register uintptr_t t asm("r0") = type; + register uintptr_t a0 asm("r1") = arg0; + asm("svc 0xab" + : /* no return */ + : "r" (t), "r" (a0)); +#else + register uintptr_t t asm("x0") = type; + register uintptr_t a0 asm("x1") = arg0; + asm("hlt 0xf000" + : /* no return */ + : "r" (t), "r" (a0)); +#endif +} + +int main(int argc, char *argv[argc]) +{ +#if defined(__arm__) + uintptr_t exit_code = 0x20026; +#else + uintptr_t exit_block[2] = {0x20026, 0}; + uintptr_t exit_code = (uintptr_t) &exit_block; +#endif + + __semi_call(SYS_WRITE0, (uintptr_t) "Hello World"); + __semi_call(SYS_REPORTEXC, exit_code); + /* if we get here we failed */ + return -1; +} From ece628fcf69cbbd4b3efb6fbd203af07609467a2 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 20 Sep 2019 18:40:39 +0100 Subject: [PATCH 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots If we're booting a Linux kernel directly into Non-Secure state on a CPU which has Secure state, then make sure we set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed to access the FPU. Otherwise an AArch32 kernel will UNDEF as soon as it tries to use the FPU. It used to not matter that we didn't do this until commit fc1120a7f5f2d4b6, where we implemented actually honouring these NSACR bits. The problem only exists for CPUs where EL3 is AArch32; the equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to not trap, 1 to trap", so the reset value of the register permits NS access, unlike NSACR. Fixes: fc1120a7f5 Fixes: https://bugs.launchpad.net/qemu/+bug/1844597 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190920174039.3916-1-peter.maydell@linaro.org --- hw/arm/boot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index bf97ef3e33..2542266054 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -754,6 +754,8 @@ static void do_cpu_reset(void *opaque) (cs != first_cpu || !info->secure_board_setup)) { /* Linux expects non-secure state */ env->cp15.scr_el3 |= SCR_NS; + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ + env->cp15.nsacr |= 3 << 10; } } From e4e34855e658b78ecac50a651cc847662ff02cfd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 23 Sep 2019 15:11:08 +0200 Subject: [PATCH 9/9] hw/arm/boot: Use the IEC binary prefix definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IEC binary prefixes ease code review: the unit is explicit. Reviewed-by: Richard Henderson Reviewed-by: Stefano Garzarella Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Message-id: 20190923131108.21459-1-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/boot.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 2542266054..c264864c11 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -575,7 +575,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, goto fail; } - if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { + if (scells < 2 && binfo->ram_size >= 4 * GiB) { /* This is user error so deserves a friendlier error message * than the failure of setprop_sized_cells would provide */ @@ -1097,7 +1097,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, * we might still make a bad choice here. */ info->initrd_start = info->loader_start + - MIN(info->ram_size / 2, 128 * 1024 * 1024); + MIN(info->ram_size / 2, 128 * MiB); if (image_high_addr) { info->initrd_start = MAX(info->initrd_start, image_high_addr); } @@ -1157,13 +1157,13 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, * * Let's play safe and prealign it to 2MB to give us some space. */ - align = 2 * 1024 * 1024; + align = 2 * MiB; } else { /* * Some 32bit kernels will trash anything in the 4K page the * initrd ends in, so make sure the DTB isn't caught up in that. */ - align = 4096; + align = 4 * KiB; } /* Place the DTB after the initrd in memory with alignment. */ @@ -1180,7 +1180,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, info->loader_start + KERNEL_ARGS_ADDR; fixupcontext[FIXUP_ARGPTR_HI] = (info->loader_start + KERNEL_ARGS_ADDR) >> 32; - if (info->ram_size >= (1ULL << 32)) { + if (info->ram_size >= 4 * GiB) { error_report("RAM size must be less than 4GB to boot" " Linux kernel using ATAGS (try passing a device tree" " using -dtb)");