mirror of https://gitee.com/openkylin/qemu.git
tcg: Optional target implementation of ORC.
Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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11
tcg/tcg-op.h
11
tcg/tcg-op.h
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@ -1715,20 +1715,31 @@ static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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#ifdef TCG_TARGET_HAS_orc_i32
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tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
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#else
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TCGv_i32 t0;
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t0 = tcg_temp_new_i32();
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tcg_gen_not_i32(t0, arg2);
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tcg_gen_or_i32(ret, arg1, t0);
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tcg_temp_free_i32(t0);
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#endif
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}
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static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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#ifdef TCG_TARGET_HAS_orc_i64
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tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
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#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
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tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
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tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
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#else
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TCGv_i64 t0;
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t0 = tcg_temp_new_i64();
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tcg_gen_not_i64(t0, arg2);
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tcg_gen_or_i64(ret, arg1, t0);
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tcg_temp_free_i64(t0);
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#endif
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}
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static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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@ -112,6 +112,9 @@ DEF2(neg_i32, 1, 1, 0, 0)
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#ifdef TCG_TARGET_HAS_andc_i32
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DEF2(andc_i32, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_orc_i32
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DEF2(orc_i32, 1, 2, 0, 0)
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#endif
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#if TCG_TARGET_REG_BITS == 64
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DEF2(mov_i64, 1, 1, 0, 0)
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@ -191,6 +194,9 @@ DEF2(neg_i64, 1, 1, 0, 0)
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#ifdef TCG_TARGET_HAS_andc_i64
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DEF2(andc_i64, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_orc_i64
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DEF2(orc_i64, 1, 2, 0, 0)
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#endif
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#endif
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/* QEMU specific */
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