mirror of https://gitee.com/openkylin/qemu.git
tcg-ppc64: Begin merging ppc32 with ppc64
Just enough to compile, assuming you edit config-host.mak manually. It will still abort at runtime, due to missing brcond2, setcond2, mulu2. Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
b31284cecf
commit
796f1a689d
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@ -514,9 +514,9 @@ static const uint32_t tcg_to_isel[] = {
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[TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
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};
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static inline void tcg_out_mov(TCGContext *s, TCGType type,
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TCGReg ret, TCGReg arg)
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static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
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{
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tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
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if (ret != arg) {
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tcg_out32(s, OR | SAB(arg, ret, arg));
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}
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@ -566,13 +566,14 @@ static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
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static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
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tcg_target_long arg)
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{
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tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
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if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
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tcg_out_movi32(s, ret, arg);
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} else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
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tcg_out32(s, ADDI | TAI(ret, 0, arg));
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tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
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} else {
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int32_t high = arg >> 32;
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int32_t high = arg >> 31 >> 1;
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tcg_out_movi32(s, ret, high);
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if (high) {
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tcg_out_shli64(s, ret, ret, 32);
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@ -1984,7 +1985,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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args[3], args[4], const_args[2]);
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break;
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#if TCG_TARGET_REG_BITS == 64
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case INDEX_op_add2_i64:
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#else
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case INDEX_op_add2_i32:
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#endif
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/* Note that the CA bit is defined based on the word size of the
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environment. So in 64-bit mode it's always carry-out of bit 63.
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The fallback code using deposit works just as well for 32-bit. */
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@ -2007,7 +2012,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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}
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break;
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#if TCG_TARGET_REG_BITS == 64
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case INDEX_op_sub2_i64:
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#else
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case INDEX_op_sub2_i32:
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#endif
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a0 = args[0], a1 = args[1];
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if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
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a0 = TCG_REG_R0;
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@ -2054,21 +2063,10 @@ static const TCGTargetOpDef ppc_op_defs[] = {
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{ INDEX_op_ld16u_i32, { "r", "r" } },
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{ INDEX_op_ld16s_i32, { "r", "r" } },
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{ INDEX_op_ld_i32, { "r", "r" } },
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{ INDEX_op_ld_i64, { "r", "r" } },
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{ INDEX_op_st8_i32, { "r", "r" } },
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{ INDEX_op_st8_i64, { "r", "r" } },
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{ INDEX_op_st16_i32, { "r", "r" } },
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{ INDEX_op_st16_i64, { "r", "r" } },
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{ INDEX_op_st_i32, { "r", "r" } },
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{ INDEX_op_st_i64, { "r", "r" } },
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{ INDEX_op_st32_i64, { "r", "r" } },
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{ INDEX_op_ld8u_i64, { "r", "r" } },
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{ INDEX_op_ld8s_i64, { "r", "r" } },
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{ INDEX_op_ld16u_i64, { "r", "r" } },
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{ INDEX_op_ld16s_i64, { "r", "r" } },
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{ INDEX_op_ld32u_i64, { "r", "r" } },
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{ INDEX_op_ld32s_i64, { "r", "r" } },
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{ INDEX_op_st8_i32, { "r", "r" } },
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{ INDEX_op_st16_i32, { "r", "r" } },
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{ INDEX_op_st_i32, { "r", "r" } },
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{ INDEX_op_add_i32, { "r", "r", "ri" } },
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{ INDEX_op_mul_i32, { "r", "r", "rI" } },
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@ -2090,11 +2088,32 @@ static const TCGTargetOpDef ppc_op_defs[] = {
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{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
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{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
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{ INDEX_op_brcond_i32, { "r", "ri" } },
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{ INDEX_op_brcond_i64, { "r", "ri" } },
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{ INDEX_op_neg_i32, { "r", "r" } },
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{ INDEX_op_not_i32, { "r", "r" } },
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{ INDEX_op_ext8s_i32, { "r", "r" } },
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{ INDEX_op_ext16s_i32, { "r", "r" } },
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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{ INDEX_op_brcond_i32, { "r", "ri" } },
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{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
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{ INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_ld8u_i64, { "r", "r" } },
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{ INDEX_op_ld8s_i64, { "r", "r" } },
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{ INDEX_op_ld16u_i64, { "r", "r" } },
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{ INDEX_op_ld16s_i64, { "r", "r" } },
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{ INDEX_op_ld32u_i64, { "r", "r" } },
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{ INDEX_op_ld32s_i64, { "r", "r" } },
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{ INDEX_op_ld_i64, { "r", "r" } },
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{ INDEX_op_st8_i64, { "r", "r" } },
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{ INDEX_op_st16_i64, { "r", "r" } },
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{ INDEX_op_st32_i64, { "r", "r" } },
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{ INDEX_op_st_i64, { "r", "r" } },
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{ INDEX_op_add_i64, { "r", "r", "rT" } },
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{ INDEX_op_sub_i64, { "r", "rI", "rT" } },
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@ -2119,36 +2138,47 @@ static const TCGTargetOpDef ppc_op_defs[] = {
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{ INDEX_op_neg_i64, { "r", "r" } },
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{ INDEX_op_not_i64, { "r", "r" } },
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{ INDEX_op_qemu_ld_i32, { "r", "L" } },
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{ INDEX_op_qemu_ld_i64, { "r", "L" } },
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{ INDEX_op_qemu_st_i32, { "S", "S" } },
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{ INDEX_op_qemu_st_i64, { "S", "S" } },
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{ INDEX_op_ext8s_i32, { "r", "r" } },
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{ INDEX_op_ext16s_i32, { "r", "r" } },
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{ INDEX_op_ext8s_i64, { "r", "r" } },
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{ INDEX_op_ext16s_i64, { "r", "r" } },
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{ INDEX_op_ext32s_i64, { "r", "r" } },
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{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
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{ INDEX_op_setcond_i64, { "r", "r", "ri" } },
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{ INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
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{ INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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{ INDEX_op_bswap16_i64, { "r", "r" } },
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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{ INDEX_op_bswap32_i64, { "r", "r" } },
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{ INDEX_op_bswap64_i64, { "r", "r" } },
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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{ INDEX_op_brcond_i64, { "r", "ri" } },
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{ INDEX_op_setcond_i64, { "r", "r", "ri" } },
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{ INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
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{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
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{ INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
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{ INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
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{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
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{ INDEX_op_muluh_i64, { "r", "r", "r" } },
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#endif
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
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{ INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
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#else
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{ INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
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{ INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
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#endif
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#if TCG_TARGET_REG_BITS == 64
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{ INDEX_op_qemu_ld_i32, { "r", "L" } },
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{ INDEX_op_qemu_st_i32, { "S", "S" } },
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{ INDEX_op_qemu_ld_i64, { "r", "L" } },
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{ INDEX_op_qemu_st_i64, { "S", "S" } },
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#elif TARGET_LONG_BITS == 32
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{ INDEX_op_qemu_ld_i32, { "r", "L" } },
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{ INDEX_op_qemu_st_i32, { "S", "S" } },
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{ INDEX_op_qemu_ld_i64, { "r", "r", "L" } },
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{ INDEX_op_qemu_st_i64, { "S", "S", "S" } },
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#else
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{ INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
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{ INDEX_op_qemu_st_i32, { "S", "S", "S" } },
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{ INDEX_op_qemu_ld_i64, { "r", "r", "L", "L" } },
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{ INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
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#endif
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{ -1 },
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};
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@ -24,6 +24,12 @@
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#ifndef TCG_TARGET_PPC64
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#define TCG_TARGET_PPC64 1
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#ifdef _ARCH_PPC64
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# define TCG_TARGET_REG_BITS 64
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#else
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# define TCG_TARGET_REG_BITS 32
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#endif
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#define TCG_TARGET_NB_REGS 32
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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@ -44,9 +50,6 @@ typedef enum {
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
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#define TCG_TARGET_HAS_ext16u_i32 0
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#define TCG_TARGET_HAS_ext8u_i64 0
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#define TCG_TARGET_HAS_ext16u_i64 0
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#define TCG_TARGET_HAS_ext32u_i64 0
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 1
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@ -65,20 +68,24 @@ typedef enum {
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#define TCG_TARGET_HAS_nor_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_trunc_shr_i32 0
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_trunc_shr_i32 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 0
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 0
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#define TCG_TARGET_HAS_ext16u_i64 0
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#define TCG_TARGET_HAS_ext32u_i64 0
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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@ -97,5 +104,6 @@ typedef enum {
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#endif
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#endif
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