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arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 

This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-14-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2018-03-01 11:05:51 +00:00 committed by Peter Maydell
parent 026e2d6ef7
commit 7a2c6e6181
1 changed files with 133 additions and 75 deletions
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58
target/arm/translate-a64.c
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@ -10247,6 +10247,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
int datasize, elements; int datasize, elements;
int pass; int pass;
TCGv_ptr fpst; TCGv_ptr fpst;
bool pairwise = false;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s); unallocated_encoding(s);
@ -10272,8 +10273,64 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
datasize = is_q ? 128 : 64; datasize = is_q ? 128 : 64;
elements = datasize / 16; elements = datasize / 16;
switch (fpopcode) {
case 0x10: /* FMAXNMP */
case 0x12: /* FADDP */
case 0x16: /* FMAXP */
case 0x18: /* FMINNMP */
case 0x1e: /* FMINP */
pairwise = true;
break;
}
fpst = get_fpstatus_ptr(true); fpst = get_fpstatus_ptr(true);
if (pairwise) {
int maxpass = is_q ? 8 : 4;
TCGv_i32 tcg_op1 = tcg_temp_new_i32();
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
TCGv_i32 tcg_res[8];
for (pass = 0; pass < maxpass; pass++) {
int passreg = pass < (maxpass / 2) ? rn : rm;
int passelt = (pass << 1) & (maxpass - 1);
read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
tcg_res[pass] = tcg_temp_new_i32();
switch (fpopcode) {
case 0x10: /* FMAXNMP */
gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
fpst);
break;
case 0x12: /* FADDP */
gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
break;
case 0x16: /* FMAXP */
gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
break;
case 0x18: /* FMINNMP */
gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
fpst);
break;
case 0x1e: /* FMINP */
gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
break;
default:
g_assert_not_reached();
}
}
for (pass = 0; pass < maxpass; pass++) {
write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
tcg_temp_free_i32(tcg_res[pass]);
}
tcg_temp_free_i32(tcg_op1);
tcg_temp_free_i32(tcg_op2);
} else {
for (pass = 0; pass < elements; pass++) { for (pass = 0; pass < elements; pass++) {
TCGv_i32 tcg_op1 = tcg_temp_new_i32(); TCGv_i32 tcg_op1 = tcg_temp_new_i32();
TCGv_i32 tcg_op2 = tcg_temp_new_i32(); TCGv_i32 tcg_op2 = tcg_temp_new_i32();
@ -10358,6 +10415,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tcg_op1); tcg_temp_free_i32(tcg_op1);
tcg_temp_free_i32(tcg_op2); tcg_temp_free_i32(tcg_op2);
} }
}
tcg_temp_free_ptr(fpst); tcg_temp_free_ptr(fpst);