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Fix sp804 dual-timer 

Properly implement dual-timer read/write for the sp804 dual timer module.
Based on ARM specs at
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html

Signed-off-by: Hans Jang <hsjang@ok-labs.com>
Signed-off-by: David Mirabito <david.mirabito@nicta.com.au>
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Chubb 2011-12-12 10:25:42 +00:00 committed by Peter Maydell
parent f18318eef8
commit 7b4252e83f
1 changed files with 36 additions and 7 deletions
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43
hw/arm_timer.c
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@ -170,9 +170,9 @@ static arm_timer_state *arm_timer_init(uint32_t freq)
} }
/* ARM PrimeCell SP804 dual timer module. /* ARM PrimeCell SP804 dual timer module.
Docs for this device don't seem to be publicly available. This * Docs at
implementation is based on guesswork, the linux kernel sources and the * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
Integrator/CP timer modules. */ */
typedef struct { typedef struct {
SysBusDevice busdev; SysBusDevice busdev;
@ -182,6 +182,13 @@ typedef struct {
qemu_irq irq; qemu_irq irq;
} sp804_state; } sp804_state;
static const uint8_t sp804_ids[] = {
/* Timer ID */
0x04, 0x18, 0x14, 0,
/* PrimeCell ID */
0xd, 0xf0, 0x05, 0xb1
};
/* Merge the IRQs from the two component devices. */ /* Merge the IRQs from the two component devices. */
static void sp804_set_irq(void *opaque, int irq, int level) static void sp804_set_irq(void *opaque, int irq, int level)
{ {
@ -196,12 +203,27 @@ static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
{ {
sp804_state *s = (sp804_state *)opaque; sp804_state *s = (sp804_state *)opaque;
/* ??? Don't know the PrimeCell ID for this device. */
if (offset < 0x20) { if (offset < 0x20) {
return arm_timer_read(s->timer[0], offset); return arm_timer_read(s->timer[0], offset);
} else { }
if (offset < 0x40) {
return arm_timer_read(s->timer[1], offset - 0x20); return arm_timer_read(s->timer[1], offset - 0x20);
} }
/* TimerPeriphID */
if (offset >= 0xfe0 && offset <= 0xffc) {
return sp804_ids[(offset - 0xfe0) >> 2];
}
switch (offset) {
/* Integration Test control registers, which we won't support */
case 0xf00: /* TimerITCR */
case 0xf04: /* TimerITOP (strictly write only but..) */
return 0;
}
hw_error("%s: Bad offset %x\n", __func__, (int)offset);
return 0;
} }
static void sp804_write(void *opaque, target_phys_addr_t offset, static void sp804_write(void *opaque, target_phys_addr_t offset,
@ -211,9 +233,16 @@ static void sp804_write(void *opaque, target_phys_addr_t offset,
if (offset < 0x20) { if (offset < 0x20) {
arm_timer_write(s->timer[0], offset, value); arm_timer_write(s->timer[0], offset, value);
} else { return;
arm_timer_write(s->timer[1], offset - 0x20, value);
} }
if (offset < 0x40) {
arm_timer_write(s->timer[1], offset - 0x20, value);
return;
}
/* Technically we could be writing to the Test Registers, but not likely */
hw_error("%s: Bad offset %x\n", __func__, (int)offset);
} }
static const MemoryRegionOps sp804_ops = { static const MemoryRegionOps sp804_ops = {