mirror of https://gitee.com/openkylin/qemu.git
exec: [tcg] Track which vCPU is performing translation and execution
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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@ -151,6 +151,7 @@ void alpha_translate_init(void)
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done_init = 1;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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for (i = 0; i < 31; i++) {
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cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
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@ -85,6 +85,7 @@ void arm_translate_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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for (i = 0; i < 16; i++) {
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cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
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@ -3374,6 +3374,7 @@ void cris_initialize_tcg(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cc_x = tcg_global_mem_new(cpu_env,
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offsetof(CPUCRISState, cc_x), "cc_x");
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cc_src = tcg_global_mem_new(cpu_env,
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@ -1250,6 +1250,7 @@ void cris_initialize_crisv10_tcg(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cc_x = tcg_global_mem_new(cpu_env,
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offsetof(CPUCRISState, cc_x), "cc_x");
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cc_src = tcg_global_mem_new(cpu_env,
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@ -8152,6 +8152,7 @@ void tcg_x86_init(void)
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initialized = true;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
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offsetof(CPUX86State, cc_op), "cc_op");
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cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
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@ -1202,6 +1202,7 @@ void lm32_translate_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
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cpu_R[i] = tcg_global_mem_new(cpu_env,
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@ -78,6 +78,7 @@ void m68k_tcg_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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#define DEFO32(name, offset) \
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QREG_##name = tcg_global_mem_new_i32(cpu_env, \
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@ -1878,6 +1878,7 @@ void mb_tcg_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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env_debug = tcg_global_mem_new(cpu_env,
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offsetof(CPUMBState, debug),
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@ -20005,6 +20005,7 @@ void mips_tcg_init(void)
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return;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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TCGV_UNUSED(cpu_gpr[0]);
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for (i = 1; i < 32; i++)
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@ -106,6 +106,7 @@ void moxie_translate_init(void)
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return;
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}
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cpu_pc = tcg_global_mem_new_i32(cpu_env,
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offsetof(CPUMoxieState, pc), "$pc");
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for (i = 0; i < 16; i++)
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@ -78,6 +78,7 @@ void openrisc_translate_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cpu_sr = tcg_global_mem_new(cpu_env,
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offsetof(CPUOpenRISCState, sr), "sr");
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env_flags = tcg_global_mem_new_i32(cpu_env,
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@ -88,6 +88,7 @@ void ppc_translate_init(void)
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return;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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p = cpu_reg_names;
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cpu_reg_names_size = sizeof(cpu_reg_names);
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@ -169,6 +169,7 @@ void s390x_translate_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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psw_addr = tcg_global_mem_new_i64(cpu_env,
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offsetof(CPUS390XState, psw.addr),
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"psw_addr");
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@ -101,6 +101,7 @@ void sh4_translate_init(void)
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return;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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for (i = 0; i < 24; i++)
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cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
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@ -5404,6 +5404,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
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inited = 1;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
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offsetof(CPUSPARCState, regwptr),
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@ -2443,6 +2443,7 @@ void tilegx_tcg_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
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for (i = 0; i < TILEGX_R_COUNT; i++) {
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cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
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@ -8835,6 +8835,7 @@ void tricore_tcg_init(void)
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return;
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}
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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/* reg init */
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for (i = 0 ; i < 16 ; i++) {
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cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
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@ -70,6 +70,7 @@ void uc32_translate_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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for (i = 0; i < 32; i++) {
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cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
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@ -219,6 +219,7 @@ void xtensa_translate_init(void)
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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tcg_ctx.tcg_env = cpu_env;
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cpu_pc = tcg_global_mem_new_i32(cpu_env,
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offsetof(CPUXtensaState, pc), "pc");
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@ -599,6 +599,10 @@ struct TCGContext {
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TBContext tb_ctx;
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/* Track which vCPU triggers events */
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CPUState *cpu; /* *_trans */
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TCGv_env tcg_env; /* *_exec */
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/* The TCGBackendData structure is private to tcg-target.inc.c. */
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struct TCGBackendData *be;
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@ -1182,7 +1182,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
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tcg_func_start(&tcg_ctx);
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tcg_ctx.cpu = ENV_GET_CPU(env);
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gen_intermediate_code(env, tb);
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tcg_ctx.cpu = NULL;
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trace_translate_block(tb, tb->pc, tb->tc_ptr);
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