mirror of https://gitee.com/openkylin/qemu.git
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -78,7 +78,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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int cpu;
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uint32_t *cells;
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char *nodename;
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char ethclk_names[] = "pclk\0hclk\0tx_clk";
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char ethclk_names[] = "pclk\0hclk";
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uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
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uint32_t uartclk_phandle;
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uint32_t hfclk_phandle, rtcclk_phandle;
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@ -263,7 +263,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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ethclk_phandle, ethclk_phandle, ethclk_phandle);
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prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
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qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
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sizeof(ethclk_names));
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qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
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@ -293,7 +293,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_UART0].base,
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0x0, memmap[SIFIVE_U_UART0].size);
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qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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prci_phandle, PRCI_CLK_TLCLK);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
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@ -78,4 +78,14 @@ typedef struct SiFiveUPRCIState {
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uint32_t clkmuxstatus;
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} SiFiveUPRCIState;
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/*
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* Clock indexes for use by Device Tree data and the PRCI driver.
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*
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* These values are from sifive-fu540-prci.h in the Linux kernel.
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*/
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#define PRCI_CLK_COREPLL 0
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#define PRCI_CLK_DDRPLL 1
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#define PRCI_CLK_GEMGXLPLL 2
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#define PRCI_CLK_TLCLK 3
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#endif /* HW_SIFIVE_U_PRCI_H */
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