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target-arm: Handle VMOV between two core and VFP single regs 

Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
pair of VFP single precision registers):

 * An incorrect condition meant these instruction patterns were being
   treated as load/store multiple, which resulted in the generation
   of bad code and a runtime segfault
 * The order of the core register pair was reversed so the values would
   go to the wrong registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-03-01 17:35:19 +00:00 committed by Aurelien Jarno
parent e095e2f3b4
commit 8387da8197
1 changed files with 5 additions and 5 deletions
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10
target-arm/translate.c
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@ -3257,7 +3257,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
break; break;
case 0xc: case 0xc:
case 0xd: case 0xd:
if (dp && (insn & 0x03e00000) == 0x00400000) { if ((insn & 0x03e00000) == 0x00400000) {
/* two-register transfer */ /* two-register transfer */
rn = (insn >> 16) & 0xf; rn = (insn >> 16) & 0xf;
rd = (insn >> 12) & 0xf; rd = (insn >> 12) & 0xf;
@ -3279,10 +3279,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
} else { } else {
gen_mov_F0_vreg(0, rm); gen_mov_F0_vreg(0, rm);
tmp = gen_vfp_mrs(); tmp = gen_vfp_mrs();
store_reg(s, rn, tmp); store_reg(s, rd, tmp);
gen_mov_F0_vreg(0, rm + 1); gen_mov_F0_vreg(0, rm + 1);
tmp = gen_vfp_mrs(); tmp = gen_vfp_mrs();
store_reg(s, rd, tmp); store_reg(s, rn, tmp);
} }
} else { } else {
/* arm->vfp */ /* arm->vfp */
@ -3294,10 +3294,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
gen_vfp_msr(tmp); gen_vfp_msr(tmp);
gen_mov_vreg_F0(0, rm * 2 + 1); gen_mov_vreg_F0(0, rm * 2 + 1);
} else { } else {
tmp = load_reg(s, rn); tmp = load_reg(s, rd);
gen_vfp_msr(tmp); gen_vfp_msr(tmp);
gen_mov_vreg_F0(0, rm); gen_mov_vreg_F0(0, rm);
tmp = load_reg(s, rd); tmp = load_reg(s, rn);
gen_vfp_msr(tmp); gen_vfp_msr(tmp);
gen_mov_vreg_F0(0, rm + 1); gen_mov_vreg_F0(0, rm + 1);
} }