openkylin
/
qemu
mirror of https://gitee.com/openkylin/qemu.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

target/microblaze: Fix width of FSR 

The exception status register is only 32-bits wide.  Do not use a
64-bit type to represent it.  Since cpu_fsr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 22:40:23 -07:00
parent 6efd55995a
commit 86017ccfbd
2 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/microblaze/cpu.h
View File

@ -240,7 +240,7 @@ struct CPUMBState {
uint32_t msr; uint32_t msr;
uint64_t ear; uint64_t ear;
uint32_t esr; uint32_t esr;
uint64_t fsr; uint32_t fsr;
uint64_t btr; uint64_t btr;
uint64_t edr; uint64_t edr;
float_status fp_status; float_status fp_status;

11
target/microblaze/translate.c
View File

@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_msr; static TCGv_i32 cpu_msr;
static TCGv_i64 cpu_ear; static TCGv_i64 cpu_ear;
static TCGv_i32 cpu_esr; static TCGv_i32 cpu_esr;
static TCGv_i64 cpu_fsr;
static TCGv_i64 cpu_btr; static TCGv_i64 cpu_btr;
static TCGv_i64 cpu_edr; static TCGv_i64 cpu_edr;
static TCGv_i32 env_imm; static TCGv_i32 env_imm;
@ -542,7 +541,8 @@ static void dec_msr(DisasContext *dc)
tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]);
break; break;
case SR_FSR: case SR_FSR:
tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]); tcg_gen_st_i32(cpu_R[dc->ra],
cpu_env, offsetof(CPUMBState, fsr));
break; break;
case SR_BTR: case SR_BTR:
tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]); tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]);
@ -583,7 +583,8 @@ static void dec_msr(DisasContext *dc)
tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr);
break; break;
case SR_FSR: case SR_FSR:
tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr); tcg_gen_ld_i32(cpu_R[dc->rd],
cpu_env, offsetof(CPUMBState, fsr));
break; break;
case SR_BTR: case SR_BTR:
tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr); tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr);
@ -1798,7 +1799,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "IN: PC=%x %s\n", qemu_fprintf(f, "IN: PC=%x %s\n",
env->pc, lookup_symbol(env->pc)); env->pc, lookup_symbol(env->pc));
qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " "
"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " "debug=%x imm=%x iflags=%x fsr=%x "
"rbtr=%" PRIx64 "\n", "rbtr=%" PRIx64 "\n",
env->msr, env->esr, env->ear, env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags, env->fsr, env->debug, env->imm, env->iflags, env->fsr,
@ -1867,8 +1868,6 @@ void mb_tcg_init(void)
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
cpu_esr = cpu_esr =
tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
cpu_fsr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
cpu_btr = cpu_btr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
cpu_edr = cpu_edr =